
Vu Anh Le
Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2818, 2825, 0, 2824, 2511 |
| Total Applications | 2999 |
| Issued Applications | 2864 |
| Pending Applications | 54 |
| Abandoned Applications | 89 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6126499
[patent_doc_number] => 20020075717
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => ' Memory architecture and decoder addressing'
[patent_app_type] => new
[patent_app_number] => 10/078620
[patent_app_country] => US
[patent_app_date] => 2002-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3689
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0075/20020075717.pdf
[firstpage_image] =>[orig_patent_app_number] => 10078620
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/078620 | Memory architecture and decoder addressing | Feb 18, 2002 | Issued |
Array
(
[id] => 1258898
[patent_doc_number] => 06667917
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-23
[patent_title] => 'System and method for identification of faulty or weak memory cells under simulated extreme operating conditions'
[patent_app_type] => B1
[patent_app_number] => 10/077837
[patent_app_country] => US
[patent_app_date] => 2002-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 7295
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/667/06667917.pdf
[firstpage_image] =>[orig_patent_app_number] => 10077837
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/077837 | System and method for identification of faulty or weak memory cells under simulated extreme operating conditions | Feb 14, 2002 | Issued |
Array
(
[id] => 6303875
[patent_doc_number] => 20020093852
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-18
[patent_title] => 'Memory device'
[patent_app_type] => new
[patent_app_number] => 10/059328
[patent_app_country] => US
[patent_app_date] => 2002-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 11614
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0093/20020093852.pdf
[firstpage_image] =>[orig_patent_app_number] => 10059328
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/059328 | Memory device | Jan 30, 2002 | Issued |
Array
(
[id] => 6013917
[patent_doc_number] => 20020101712
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-08-01
[patent_title] => 'Diskette type electronic device'
[patent_app_type] => new
[patent_app_number] => 10/052333
[patent_app_country] => US
[patent_app_date] => 2002-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2289
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0101/20020101712.pdf
[firstpage_image] =>[orig_patent_app_number] => 10052333
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/052333 | Diskette type electronic device | Jan 22, 2002 | Abandoned |
Array
(
[id] => 1425924
[patent_doc_number] => 06525984
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-02-25
[patent_title] => 'Semiconductor integrated circuit device having hierarchical power source arrangement'
[patent_app_type] => B2
[patent_app_number] => 10/047104
[patent_app_country] => US
[patent_app_date] => 2002-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 52
[patent_figures_cnt] => 68
[patent_no_of_words] => 50605
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/525/06525984.pdf
[firstpage_image] =>[orig_patent_app_number] => 10047104
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/047104 | Semiconductor integrated circuit device having hierarchical power source arrangement | Jan 16, 2002 | Issued |
Array
(
[id] => 1182041
[patent_doc_number] => 06747903
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-08
[patent_title] => 'Configurable decoder for addressing a memory'
[patent_app_type] => B1
[patent_app_number] => 10/046939
[patent_app_country] => US
[patent_app_date] => 2002-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 33
[patent_no_of_words] => 13875
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/747/06747903.pdf
[firstpage_image] =>[orig_patent_app_number] => 10046939
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/046939 | Configurable decoder for addressing a memory | Jan 13, 2002 | Issued |
Array
(
[id] => 6722439
[patent_doc_number] => 20030056129
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-20
[patent_title] => 'Conditional pre-charge method and system'
[patent_app_type] => new
[patent_app_number] => 10/043933
[patent_app_country] => US
[patent_app_date] => 2002-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6260
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0056/20030056129.pdf
[firstpage_image] =>[orig_patent_app_number] => 10043933
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/043933 | Conditional pre-charge method and system | Jan 10, 2002 | Issued |
Array
(
[id] => 1223546
[patent_doc_number] => 06704240
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-09
[patent_title] => 'Predecoder control circuit'
[patent_app_type] => B2
[patent_app_number] => 10/029257
[patent_app_country] => US
[patent_app_date] => 2001-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4786
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/704/06704240.pdf
[firstpage_image] =>[orig_patent_app_number] => 10029257
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/029257 | Predecoder control circuit | Dec 27, 2001 | Issued |
Array
(
[id] => 6759923
[patent_doc_number] => 20030123284
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-03
[patent_title] => 'Method and apparatus to operate a memory cell'
[patent_app_type] => new
[patent_app_number] => 10/034331
[patent_app_country] => US
[patent_app_date] => 2001-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4927
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 32
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0123/20030123284.pdf
[firstpage_image] =>[orig_patent_app_number] => 10034331
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/034331 | Method and apparatus to operate a memory cell | Dec 27, 2001 | Issued |
Array
(
[id] => 7623020
[patent_doc_number] => 06687145
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-03
[patent_title] => 'Static random access memory cell and method'
[patent_app_type] => B2
[patent_app_number] => 10/028199
[patent_app_country] => US
[patent_app_date] => 2001-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3218
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 12
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/687/06687145.pdf
[firstpage_image] =>[orig_patent_app_number] => 10028199
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/028199 | Static random access memory cell and method | Dec 19, 2001 | Issued |
Array
(
[id] => 7623006
[patent_doc_number] => 06687159
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-03
[patent_title] => 'Method of programming a plurality of memory cells connected in parallel, and a programming circuit therefor'
[patent_app_type] => B2
[patent_app_number] => 10/036337
[patent_app_country] => US
[patent_app_date] => 2001-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4086
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/687/06687159.pdf
[firstpage_image] =>[orig_patent_app_number] => 10036337
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/036337 | Method of programming a plurality of memory cells connected in parallel, and a programming circuit therefor | Dec 18, 2001 | Issued |
Array
(
[id] => 1238795
[patent_doc_number] => 06690604
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-10
[patent_title] => 'Register files and caches with digital sub-threshold leakage current calibration'
[patent_app_type] => B2
[patent_app_number] => 10/024901
[patent_app_country] => US
[patent_app_date] => 2001-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2181
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/690/06690604.pdf
[firstpage_image] =>[orig_patent_app_number] => 10024901
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/024901 | Register files and caches with digital sub-threshold leakage current calibration | Dec 17, 2001 | Issued |
Array
(
[id] => 7627335
[patent_doc_number] => 06807106
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-19
[patent_title] => 'Hybrid density memory card'
[patent_app_type] => B2
[patent_app_number] => 10/017035
[patent_app_country] => US
[patent_app_date] => 2001-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 5029
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 13
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/807/06807106.pdf
[firstpage_image] =>[orig_patent_app_number] => 10017035
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/017035 | Hybrid density memory card | Dec 13, 2001 | Issued |
Array
(
[id] => 1418937
[patent_doc_number] => 06535435
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-18
[patent_title] => 'Reference voltage generator permitting stable operation'
[patent_app_type] => B2
[patent_app_number] => 10/012522
[patent_app_country] => US
[patent_app_date] => 2001-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 36
[patent_no_of_words] => 24542
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 270
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/535/06535435.pdf
[firstpage_image] =>[orig_patent_app_number] => 10012522
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/012522 | Reference voltage generator permitting stable operation | Dec 11, 2001 | Issued |
Array
(
[id] => 1275843
[patent_doc_number] => 06654294
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-25
[patent_title] => 'Flash memory device'
[patent_app_type] => B2
[patent_app_number] => 10/006893
[patent_app_country] => US
[patent_app_date] => 2001-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4557
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/654/06654294.pdf
[firstpage_image] =>[orig_patent_app_number] => 10006893
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/006893 | Flash memory device | Dec 9, 2001 | Issued |
Array
(
[id] => 6868766
[patent_doc_number] => 20030081455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-01
[patent_title] => 'Floating gate programmable cell array for standard CMOS'
[patent_app_type] => new
[patent_app_number] => 10/005805
[patent_app_country] => US
[patent_app_date] => 2001-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2853
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0081/20030081455.pdf
[firstpage_image] =>[orig_patent_app_number] => 10005805
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/005805 | Floating gate programmable cell array for standard CMOS | Dec 4, 2001 | Issued |
Array
(
[id] => 6584816
[patent_doc_number] => 20020041535
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-04-11
[patent_title] => 'Full page increment/decrement burst for DDR SDRAM/SGRAM'
[patent_app_type] => new
[patent_app_number] => 10/004672
[patent_app_country] => US
[patent_app_date] => 2001-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4899
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0041/20020041535.pdf
[firstpage_image] =>[orig_patent_app_number] => 10004672
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/004672 | Full page increment/decrement burst for DDR SDRAM/SGRAM | Dec 3, 2001 | Issued |
Array
(
[id] => 1582494
[patent_doc_number] => 06449193
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-10
[patent_title] => 'Burst access memory system'
[patent_app_type] => B1
[patent_app_number] => 09/998727
[patent_app_country] => US
[patent_app_date] => 2001-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2686
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/449/06449193.pdf
[firstpage_image] =>[orig_patent_app_number] => 09998727
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/998727 | Burst access memory system | Dec 2, 2001 | Issued |
Array
(
[id] => 1223544
[patent_doc_number] => 06704239
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-09
[patent_title] => 'Non-volatile semiconductor memory device'
[patent_app_type] => B2
[patent_app_number] => 09/997533
[patent_app_country] => US
[patent_app_date] => 2001-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 12660
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/704/06704239.pdf
[firstpage_image] =>[orig_patent_app_number] => 09997533
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/997533 | Non-volatile semiconductor memory device | Nov 28, 2001 | Issued |
Array
(
[id] => 1470090
[patent_doc_number] => 06459652
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Semiconductor memory device having echo clock path'
[patent_app_type] => B1
[patent_app_number] => 09/996225
[patent_app_country] => US
[patent_app_date] => 2001-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3858
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/459/06459652.pdf
[firstpage_image] =>[orig_patent_app_number] => 09996225
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/996225 | Semiconductor memory device having echo clock path | Nov 27, 2001 | Issued |