
Vu Anh Le
Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2818, 2825, 0, 2824, 2511 |
| Total Applications | 2999 |
| Issued Applications | 2864 |
| Pending Applications | 54 |
| Abandoned Applications | 89 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1457762
[patent_doc_number] => 06462982
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-08
[patent_title] => 'Magnetic random access memory having voltage control circuitry for maintaining sense lines at constant low voltages'
[patent_app_type] => B1
[patent_app_number] => 09/962325
[patent_app_country] => US
[patent_app_date] => 2001-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7665
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/462/06462982.pdf
[firstpage_image] =>[orig_patent_app_number] => 09962325
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/962325 | Magnetic random access memory having voltage control circuitry for maintaining sense lines at constant low voltages | Sep 25, 2001 | Issued |
Array
(
[id] => 5934652
[patent_doc_number] => 20020060934
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-23
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF IDENTIFYING PROGRAMMED DEFECTIVE ADDRESS THEREOF'
[patent_app_type] => new
[patent_app_number] => 09/955635
[patent_app_country] => US
[patent_app_date] => 2001-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7520
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0060/20020060934.pdf
[firstpage_image] =>[orig_patent_app_number] => 09955635
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/955635 | Semiconductor memory device and method of identifying programmed defective address thereof | Sep 18, 2001 | Issued |
Array
(
[id] => 6400322
[patent_doc_number] => 20020036925
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-28
[patent_title] => 'Non-volatile semiconductor memory'
[patent_app_type] => new
[patent_app_number] => 09/953227
[patent_app_country] => US
[patent_app_date] => 2001-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 14696
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0036/20020036925.pdf
[firstpage_image] =>[orig_patent_app_number] => 09953227
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/953227 | Non-volatile semiconductor memory | Sep 16, 2001 | Issued |
Array
(
[id] => 6400253
[patent_doc_number] => 20020036916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-28
[patent_title] => 'Integrated memory having memory cells and buffer capacitors'
[patent_app_type] => new
[patent_app_number] => 09/953729
[patent_app_country] => US
[patent_app_date] => 2001-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2386
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0036/20020036916.pdf
[firstpage_image] =>[orig_patent_app_number] => 09953729
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/953729 | Integrated memory having memory cells and buffer capacitors | Sep 16, 2001 | Issued |
Array
(
[id] => 5984047
[patent_doc_number] => 20020097612
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-25
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => new
[patent_app_number] => 09/953555
[patent_app_country] => US
[patent_app_date] => 2001-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4460
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0097/20020097612.pdf
[firstpage_image] =>[orig_patent_app_number] => 09953555
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/953555 | Semiconductor integrated circuit | Sep 16, 2001 | Issued |
Array
(
[id] => 5800022
[patent_doc_number] => 20020008992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-24
[patent_title] => 'Semiconductor non-volatile storage'
[patent_app_type] => new
[patent_app_number] => 09/951979
[patent_app_country] => US
[patent_app_date] => 2001-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 9641
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 235
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0008/20020008992.pdf
[firstpage_image] =>[orig_patent_app_number] => 09951979
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/951979 | Semiconductor non-volatile storage | Sep 13, 2001 | Issued |
Array
(
[id] => 1603876
[patent_doc_number] => 06434059
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-13
[patent_title] => 'Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts'
[patent_app_type] => B1
[patent_app_number] => 09/944238
[patent_app_country] => US
[patent_app_date] => 2001-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2384
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/434/06434059.pdf
[firstpage_image] =>[orig_patent_app_number] => 09944238
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/944238 | Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts | Aug 29, 2001 | Issued |
Array
(
[id] => 6489309
[patent_doc_number] => 20020024872
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-28
[patent_title] => 'Full page increment/decrement burst for DDR SDRAM/SGRAM'
[patent_app_type] => new
[patent_app_number] => 09/940915
[patent_app_country] => US
[patent_app_date] => 2001-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4511
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20020024872.pdf
[firstpage_image] =>[orig_patent_app_number] => 09940915
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/940915 | Full page increment/decrement burst for DDR SDRAM/SGRAM | Aug 27, 2001 | Issued |
Array
(
[id] => 1538538
[patent_doc_number] => 06490193
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-03
[patent_title] => 'Forming and storing data in a memory cell'
[patent_app_type] => B1
[patent_app_number] => 09/938027
[patent_app_country] => US
[patent_app_date] => 2001-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2948
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/490/06490193.pdf
[firstpage_image] =>[orig_patent_app_number] => 09938027
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/938027 | Forming and storing data in a memory cell | Aug 21, 2001 | Issued |
Array
(
[id] => 6137885
[patent_doc_number] => 20020000624
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-03
[patent_title] => 'Semiconductor device'
[patent_app_type] => new
[patent_app_number] => 09/933815
[patent_app_country] => US
[patent_app_date] => 2001-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 13780
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0000/20020000624.pdf
[firstpage_image] =>[orig_patent_app_number] => 09933815
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/933815 | Semiconductor memory device with over-driving sense amplifier | Aug 21, 2001 | Issued |
Array
(
[id] => 1550278
[patent_doc_number] => 06445623
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Charge pumps with current sources for regulation'
[patent_app_type] => B1
[patent_app_number] => 09/934931
[patent_app_country] => US
[patent_app_date] => 2001-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 6774
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/445/06445623.pdf
[firstpage_image] =>[orig_patent_app_number] => 09934931
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/934931 | Charge pumps with current sources for regulation | Aug 21, 2001 | Issued |
Array
(
[id] => 5998459
[patent_doc_number] => 20020027815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-07
[patent_title] => 'Cancellation of redundant elements with a cancel bank'
[patent_app_type] => new
[patent_app_number] => 09/930019
[patent_app_country] => US
[patent_app_date] => 2001-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3491
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20020027815.pdf
[firstpage_image] =>[orig_patent_app_number] => 09930019
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/930019 | Cancellation of redundant elements with a cancel bank | Aug 14, 2001 | Issued |
Array
(
[id] => 1417179
[patent_doc_number] => 06538957
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-25
[patent_title] => 'Apparatus and method for distributing a clock signal on a large scale integrated circuit'
[patent_app_type] => B2
[patent_app_number] => 09/929633
[patent_app_country] => US
[patent_app_date] => 2001-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 5294
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/538/06538957.pdf
[firstpage_image] =>[orig_patent_app_number] => 09929633
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/929633 | Apparatus and method for distributing a clock signal on a large scale integrated circuit | Aug 13, 2001 | Issued |
Array
(
[id] => 6400269
[patent_doc_number] => 20020036919
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-28
[patent_title] => 'Circuit selection of magnetic memory cells and related cell structures'
[patent_app_type] => new
[patent_app_number] => 09/929435
[patent_app_country] => US
[patent_app_date] => 2001-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 15622
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0036/20020036919.pdf
[firstpage_image] =>[orig_patent_app_number] => 09929435
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/929435 | Circuit selection of magnetic memory cells and related cell structures | Aug 13, 2001 | Issued |
Array
(
[id] => 1599644
[patent_doc_number] => 06385083
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-07
[patent_title] => 'MRAM device including offset conductors'
[patent_app_type] => B1
[patent_app_number] => 09/920225
[patent_app_country] => US
[patent_app_date] => 2001-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2427
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/385/06385083.pdf
[firstpage_image] =>[orig_patent_app_number] => 09920225
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/920225 | MRAM device including offset conductors | Jul 31, 2001 | Issued |
Array
(
[id] => 1546811
[patent_doc_number] => 06373744
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-16
[patent_title] => 'Ferroelectric memory'
[patent_app_type] => B1
[patent_app_number] => 09/911831
[patent_app_country] => US
[patent_app_date] => 2001-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8662
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/373/06373744.pdf
[firstpage_image] =>[orig_patent_app_number] => 09911831
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/911831 | Ferroelectric memory | Jul 24, 2001 | Issued |
Array
(
[id] => 5966275
[patent_doc_number] => 20020089879
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-11
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE OF LOW POWER CONSUMPTION'
[patent_app_type] => new
[patent_app_number] => 09/911729
[patent_app_country] => US
[patent_app_date] => 2001-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 19492
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0089/20020089879.pdf
[firstpage_image] =>[orig_patent_app_number] => 09911729
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/911729 | Semiconductor memory device of low power consumption | Jul 24, 2001 | Issued |
Array
(
[id] => 1582533
[patent_doc_number] => 06449200
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-10
[patent_title] => 'Duty-cycle-efficient SRAM cell test'
[patent_app_type] => B1
[patent_app_number] => 09/907325
[patent_app_country] => US
[patent_app_date] => 2001-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 4468
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/449/06449200.pdf
[firstpage_image] =>[orig_patent_app_number] => 09907325
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/907325 | Duty-cycle-efficient SRAM cell test | Jul 16, 2001 | Issued |
Array
(
[id] => 7077852
[patent_doc_number] => 20010040821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-15
[patent_title] => 'Nonvolatile semiconductor memory device'
[patent_app_type] => new
[patent_app_number] => 09/899290
[patent_app_country] => US
[patent_app_date] => 2001-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 98
[patent_figures_cnt] => 98
[patent_no_of_words] => 67897
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0040/20010040821.pdf
[firstpage_image] =>[orig_patent_app_number] => 09899290
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/899290 | Nonvolatile semiconductor memory device | Jul 5, 2001 | Issued |
Array
(
[id] => 1564316
[patent_doc_number] => 06438057
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-20
[patent_title] => 'DRAM refresh timing adjustment device, system and method'
[patent_app_type] => B1
[patent_app_number] => 09/900626
[patent_app_country] => US
[patent_app_date] => 2001-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 2907
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/438/06438057.pdf
[firstpage_image] =>[orig_patent_app_number] => 09900626
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/900626 | DRAM refresh timing adjustment device, system and method | Jul 5, 2001 | Issued |