Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
09/843165 Electrically programmable and erasable nonvolatile semiconductor memory device and operating method therefor Apr 26, 2001 Abandoned
Array ( [id] => 6466474 [patent_doc_number] => 20020021581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Source and drain sensing' [patent_app_type] => new [patent_app_number] => 09/840533 [patent_app_country] => US [patent_app_date] => 2001-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5124 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20020021581.pdf [firstpage_image] =>[orig_patent_app_number] => 09840533 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/840533
Source and drain sensing Apr 22, 2001 Issued
Array ( [id] => 1418705 [patent_doc_number] => 06535416 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Magnetic memory coincident thermal pulse data storage' [patent_app_type] => B1 [patent_app_number] => 09/673827 [patent_app_country] => US [patent_app_date] => 2001-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8336 [patent_no_of_claims] => 79 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535416.pdf [firstpage_image] =>[orig_patent_app_number] => 09673827 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/673827
Magnetic memory coincident thermal pulse data storage Apr 22, 2001 Issued
Array ( [id] => 7635468 [patent_doc_number] => 06381194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-30 [patent_title] => 'OUTPUT CIRCUIT FOR A DOUBLE DATA RATE DYNAMIC RANDOM ACCESS MEMORY, DOUBLE DATA RATE DYNAMIC RANDOM ACCESS MEMORY, METHOD OF CLOCKING DATA OUT FROM A DOUBLE DATA RATE DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF PROVIDING A DATA STROBE SIGNAL' [patent_app_type] => B2 [patent_app_number] => 09/838861 [patent_app_country] => US [patent_app_date] => 2001-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5663 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381194.pdf [firstpage_image] =>[orig_patent_app_number] => 09838861 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/838861
OUTPUT CIRCUIT FOR A DOUBLE DATA RATE DYNAMIC RANDOM ACCESS MEMORY, DOUBLE DATA RATE DYNAMIC RANDOM ACCESS MEMORY, METHOD OF CLOCKING DATA OUT FROM A DOUBLE DATA RATE DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF PROVIDING A DATA STROBE SIGNAL Apr 19, 2001 Issued
Array ( [id] => 7635498 [patent_doc_number] => 06381164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Low profile, high density memory system' [patent_app_type] => B1 [patent_app_number] => 09/835123 [patent_app_country] => US [patent_app_date] => 2001-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6046 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381164.pdf [firstpage_image] =>[orig_patent_app_number] => 09835123 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/835123
Low profile, high density memory system Apr 12, 2001 Issued
Array ( [id] => 6893566 [patent_doc_number] => 20010015932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics' [patent_app_type] => new [patent_app_number] => 09/832916 [patent_app_country] => US [patent_app_date] => 2001-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 85 [patent_figures_cnt] => 85 [patent_no_of_words] => 28897 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015932.pdf [firstpage_image] =>[orig_patent_app_number] => 09832916 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/832916
Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics Apr 11, 2001 Issued
Array ( [id] => 1590002 [patent_doc_number] => 06359820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-03-19 [patent_title] => 'Integrated memory and method for checking the operation of memory cells in an integrated memory' [patent_app_type] => B2 [patent_app_number] => 09/826233 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4634 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359820.pdf [firstpage_image] =>[orig_patent_app_number] => 09826233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/826233
Integrated memory and method for checking the operation of memory cells in an integrated memory Apr 3, 2001 Issued
Array ( [id] => 1368060 [patent_doc_number] => 06577526 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Magnetoresistive element and the use thereof as storage element in a storage cell array' [patent_app_type] => B1 [patent_app_number] => 09/806617 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4646 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/577/06577526.pdf [firstpage_image] =>[orig_patent_app_number] => 09806617 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/806617
Magnetoresistive element and the use thereof as storage element in a storage cell array Mar 29, 2001 Issued
Array ( [id] => 6882156 [patent_doc_number] => 20010048628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Method of controlling line memory' [patent_app_type] => new [patent_app_number] => 09/823827 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4790 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20010048628.pdf [firstpage_image] =>[orig_patent_app_number] => 09823827 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823827
Method of controlling line memory Mar 29, 2001 Issued
Array ( [id] => 6893547 [patent_doc_number] => 20010015913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Non-volatile semiconductor memory device and data programming method' [patent_app_type] => new [patent_app_number] => 09/823525 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 25138 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015913.pdf [firstpage_image] =>[orig_patent_app_number] => 09823525 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823525
Non-volatile semiconductor memory device and data programming method Mar 29, 2001 Issued
Array ( [id] => 5903599 [patent_doc_number] => 20020141251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Method and circuit for processing output data in pipelined circuits' [patent_app_type] => new [patent_app_number] => 09/823325 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7498 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20020141251.pdf [firstpage_image] =>[orig_patent_app_number] => 09823325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823325
Method and circuit for processing output data in pipelined circuits Mar 28, 2001 Issued
Array ( [id] => 1473329 [patent_doc_number] => 06407958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-18 [patent_title] => 'Semiconductor integrated circuit device with split hierarchical power supply structure' [patent_app_type] => B2 [patent_app_number] => 09/817032 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 130 [patent_no_of_words] => 31894 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407958.pdf [firstpage_image] =>[orig_patent_app_number] => 09817032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817032
Semiconductor integrated circuit device with split hierarchical power supply structure Mar 26, 2001 Issued
Array ( [id] => 1478412 [patent_doc_number] => 06388908 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Recording system, data recording device, memory device, and data recording method' [patent_app_type] => B1 [patent_app_number] => 09/806133 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 6412 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388908.pdf [firstpage_image] =>[orig_patent_app_number] => 09806133 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/806133
Recording system, data recording device, memory device, and data recording method Mar 25, 2001 Issued
Array ( [id] => 6888941 [patent_doc_number] => 20010024396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Integrated memory having a bit line reference voltage, and a method for producing the bit line reference voltage' [patent_app_type] => new [patent_app_number] => 09/816925 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3575 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20010024396.pdf [firstpage_image] =>[orig_patent_app_number] => 09816925 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/816925
Integrated memory having a bit line reference voltage, and a method for producing the bit line reference voltage Mar 22, 2001 Issued
Array ( [id] => 1555899 [patent_doc_number] => 06349049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'High speed low power content addressable memory' [patent_app_type] => B1 [patent_app_number] => 09/815227 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4074 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349049.pdf [firstpage_image] =>[orig_patent_app_number] => 09815227 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/815227
High speed low power content addressable memory Mar 21, 2001 Issued
Array ( [id] => 1411756 [patent_doc_number] => 06532182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-11 [patent_title] => 'Semiconductor memory production system and semiconductor memory production method' [patent_app_type] => B2 [patent_app_number] => 09/811529 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 32 [patent_no_of_words] => 18130 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532182.pdf [firstpage_image] =>[orig_patent_app_number] => 09811529 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811529
Semiconductor memory production system and semiconductor memory production method Mar 19, 2001 Issued
Array ( [id] => 7642971 [patent_doc_number] => 06430074 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Selective look-ahead match line pre-charging in a partitioned content addressable memory array' [patent_app_type] => B1 [patent_app_number] => 09/813900 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 11874 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430074.pdf [firstpage_image] =>[orig_patent_app_number] => 09813900 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813900
Selective look-ahead match line pre-charging in a partitioned content addressable memory array Mar 19, 2001 Issued
Array ( [id] => 1536901 [patent_doc_number] => 06411555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'REFERENCE CHARGE GENERATOR, A METHOD FOR PROVIDING A REFERENCE CHARGE FROM A REFERENCE CHARGE GENERATOR, A METHOD OF OPERATING A REFERENCE CHARGE GENERATOR AND A DRAM MEMORY CIRCUIT FORMED USING MEMORY CELLS HAVING AN AREA OF 6F2' [patent_app_type] => B1 [patent_app_number] => 09/812729 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4993 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411555.pdf [firstpage_image] =>[orig_patent_app_number] => 09812729 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812729
REFERENCE CHARGE GENERATOR, A METHOD FOR PROVIDING A REFERENCE CHARGE FROM A REFERENCE CHARGE GENERATOR, A METHOD OF OPERATING A REFERENCE CHARGE GENERATOR AND A DRAM MEMORY CIRCUIT FORMED USING MEMORY CELLS HAVING AN AREA OF 6F2 Mar 18, 2001 Issued
Array ( [id] => 5840253 [patent_doc_number] => 20020130348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => '6F2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6F2 dram array and a method of isolating a single row of memory cells in a 6F2 dram array' [patent_app_type] => new [patent_app_number] => 09/810933 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5318 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20020130348.pdf [firstpage_image] =>[orig_patent_app_number] => 09810933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/810933
6F2 DRAM ARRAY, A DRAM ARRAY FORMED ON A SEMICONDUCTIVE SUBSTRATE, A METHOD OF FORMING MEMORY CELLS IN A 6F2 DRAM ARRAY AND A METHOD OF ISOLATING A SINGLE ROW OF MEMORY CELLS IN A 6F2 DRAM ARRAY Mar 15, 2001 Issued
Array ( [id] => 1358528 [patent_doc_number] => 06580650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-17 [patent_title] => 'DRAM word line voltage control to insure full cell writeback level' [patent_app_type] => B2 [patent_app_number] => 09/810325 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 5470 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/580/06580650.pdf [firstpage_image] =>[orig_patent_app_number] => 09810325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/810325
DRAM word line voltage control to insure full cell writeback level Mar 15, 2001 Issued
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