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Vuthe Siek

Examiner (ID: 4172, Phone: (571)272-1906 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2768, 2764, 2825, 2763, 2304, 2851
Total Applications
1837
Issued Applications
1629
Pending Applications
46
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16972668 [patent_doc_number] => 11068641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-20 [patent_title] => Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture [patent_app_type] => utility [patent_app_number] => 17/192302 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10376 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192302 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192302
Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture Mar 3, 2021 Issued
Array ( [id] => 17253201 [patent_doc_number] => 11188694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Dynamic simulation method of circulating temperature variation in RMR subsea pump mud-lift drilling system [patent_app_type] => utility [patent_app_number] => 17/147418 [patent_app_country] => US [patent_app_date] => 2021-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3990 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 903 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147418 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147418
Dynamic simulation method of circulating temperature variation in RMR subsea pump mud-lift drilling system Jan 11, 2021 Issued
Array ( [id] => 16692761 [patent_doc_number] => 20210075240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => POWER MANAGEMENT SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/951842 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951842 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/951842
Power management system and operating method thereof Nov 17, 2020 Issued
Array ( [id] => 17424810 [patent_doc_number] => 11258277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Power management system and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/951862 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7824 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951862 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/951862
Power management system and operating method thereof Nov 17, 2020 Issued
Array ( [id] => 16439389 [patent_doc_number] => 20200356715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => SYSTEM FOR PRODUCING A DATA STREAM ON THE BASIS OF REDUNDANT INFORMATION [patent_app_type] => utility [patent_app_number] => 16/937129 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937129 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937129
System for producing a data stream on the basis of redundant information Jul 22, 2020 Issued
Array ( [id] => 17223797 [patent_doc_number] => 11176299 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-16 [patent_title] => Analysis of signal transitions in feedback circuits [patent_app_type] => utility [patent_app_number] => 16/929235 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929235 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/929235
Analysis of signal transitions in feedback circuits Jul 14, 2020 Issued
Array ( [id] => 16300073 [patent_doc_number] => 20200285796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => REGION BASED SHRINKING METHODOLOGY FOR INTEGRATED CIRCUIT LAYOUT MIGRATION [patent_app_type] => utility [patent_app_number] => 16/880389 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880389 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/880389
Region based shrinking methodology for integrated circuit layout migration May 20, 2020 Issued
Array ( [id] => 17223803 [patent_doc_number] => 11176305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Method and system for sigma-based timing optimization [patent_app_type] => utility [patent_app_number] => 16/878376 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6122 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878376 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878376
Method and system for sigma-based timing optimization May 18, 2020 Issued
Array ( [id] => 16424103 [patent_doc_number] => 20200349301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => Importance-Directed Geometric Simplification System and Method [patent_app_type] => utility [patent_app_number] => 16/866103 [patent_app_country] => US [patent_app_date] => 2020-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866103 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/866103
Importance-directed geometric simplification system and method May 3, 2020 Issued
Array ( [id] => 17492530 [patent_doc_number] => 11281835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Cell layout and structure [patent_app_type] => utility [patent_app_number] => 16/860714 [patent_app_country] => US [patent_app_date] => 2020-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 136 [patent_figures_cnt] => 145 [patent_no_of_words] => 17610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860714 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/860714
Cell layout and structure Apr 27, 2020 Issued
Array ( [id] => 17164214 [patent_doc_number] => 11150306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => State of charge estimation device [patent_app_type] => utility [patent_app_number] => 16/824757 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6852 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824757 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/824757
State of charge estimation device Mar 19, 2020 Issued
Array ( [id] => 17017422 [patent_doc_number] => 11087064 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-10 [patent_title] => System and method for analyzing one or more electromigration rules associated with an electronic circuit design [patent_app_type] => utility [patent_app_number] => 16/817924 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16817924 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/817924
System and method for analyzing one or more electromigration rules associated with an electronic circuit design Mar 12, 2020 Issued
Array ( [id] => 16863050 [patent_doc_number] => 11021784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Method of mask layout [patent_app_type] => utility [patent_app_number] => 16/816276 [patent_app_country] => US [patent_app_date] => 2020-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16816276 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/816276
Method of mask layout Mar 11, 2020 Issued
Array ( [id] => 16958198 [patent_doc_number] => 11062069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-13 [patent_title] => Bounded deadlock check [patent_app_type] => utility [patent_app_number] => 16/815044 [patent_app_country] => US [patent_app_date] => 2020-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4194 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16815044 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/815044
Bounded deadlock check Mar 10, 2020 Issued
Array ( [id] => 17225155 [patent_doc_number] => 11177668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Managing top-off charging and discharge testing of battery packs to optimize capacity [patent_app_type] => utility [patent_app_number] => 16/807443 [patent_app_country] => US [patent_app_date] => 2020-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9457 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807443 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/807443
Managing top-off charging and discharge testing of battery packs to optimize capacity Mar 2, 2020 Issued
Array ( [id] => 16096157 [patent_doc_number] => 20200202065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => INTEGRATED CIRCUIT METHODS USING SINGLE-PIN IMAGINARY DEVICES [patent_app_type] => utility [patent_app_number] => 16/806417 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806417 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/806417
Integrated circuit methods using single-pin imaginary devices Mar 1, 2020 Issued
Array ( [id] => 16020961 [patent_doc_number] => 20200185324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => SYSTEM FOR LAYOUT DESIGN OF STRUCTURE WITH INTER-LAYER VIAS [patent_app_type] => utility [patent_app_number] => 16/791840 [patent_app_country] => US [patent_app_date] => 2020-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16791840 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/791840
System for layout design of structure with inter layer vias Feb 13, 2020 Issued
Array ( [id] => 16300070 [patent_doc_number] => 20200285793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => SIMULATION APPARATUS, DESCRIPTION CONVERSION METHOD AND SIMULATION METHOD [patent_app_type] => utility [patent_app_number] => 16/789664 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16789664 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/789664
Simulation apparatus, description conversion method and simulation method Feb 12, 2020 Issued
Array ( [id] => 16980225 [patent_doc_number] => 20210224462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => YIELD IMPROVING LEAF CELLS OPTIMIZATION FOR SEMICONDUCTOR NETLISTS [patent_app_type] => utility [patent_app_number] => 16/747009 [patent_app_country] => US [patent_app_date] => 2020-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747009 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747009
Yield improving leaf cells optimization for semiconductor netlists Jan 19, 2020 Issued
Array ( [id] => 16980212 [patent_doc_number] => 20210224449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => PREVENTION OF FRONT-SIDE PROBING ATTACKS [patent_app_type] => utility [patent_app_number] => 16/745744 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16745744 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/745744
Prevention of front-side probing attacks Jan 16, 2020 Issued
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