Search

Vuthe Siek

Examiner (ID: 4172, Phone: (571)272-1906 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2768, 2764, 2825, 2763, 2304, 2851
Total Applications
1837
Issued Applications
1629
Pending Applications
46
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11946412 [patent_doc_number] => 20170250563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'WIRELESS CHARGING APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/592432 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11598 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592432 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/592432
Wireless charging apparatus May 10, 2017 Issued
Array ( [id] => 14669921 [patent_doc_number] => 10372862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Systems and methods for layout objects selection and replication via a graphic-based layout editor [patent_app_type] => utility [patent_app_number] => 15/589935 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 4395 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589935 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589935
Systems and methods for layout objects selection and replication via a graphic-based layout editor May 7, 2017 Issued
Array ( [id] => 14523977 [patent_doc_number] => 10339251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Method to improve transistor matching [patent_app_type] => utility [patent_app_number] => 15/495016 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2241 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15495016 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/495016
Method to improve transistor matching Apr 23, 2017 Issued
Array ( [id] => 17439466 [patent_doc_number] => 11264811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Efficiency based battery configurations [patent_app_type] => utility [patent_app_number] => 16/077339 [patent_app_country] => US [patent_app_date] => 2017-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6061 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16077339 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/077339
Efficiency based battery configurations Apr 20, 2017 Issued
Array ( [id] => 11839009 [patent_doc_number] => 20170220729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'Directed Self-Assembly-Aware Layout Decomposition For Multiple Patterning' [patent_app_type] => utility [patent_app_number] => 15/486839 [patent_app_country] => US [patent_app_date] => 2017-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15486839 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/486839
Directed Self-Assembly-Aware Layout Decomposition For Multiple Patterning Apr 12, 2017 Abandoned
Array ( [id] => 11760780 [patent_doc_number] => 20170207649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'POWER RECEIVING APPARATUS, METHOD FOR CONTROLLING POWER RECEIVING APPARATUS, AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 15/477838 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12698 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477838 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477838
Power receiving apparatus, method for controlling power receiving apparatus, and storage medium Apr 2, 2017 Issued
Array ( [id] => 11718273 [patent_doc_number] => 20170186772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section' [patent_app_type] => utility [patent_app_number] => 15/457997 [patent_app_country] => US [patent_app_date] => 2017-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 76 [patent_figures_cnt] => 76 [patent_no_of_words] => 33178 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15457997 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/457997
Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section Mar 12, 2017 Abandoned
Array ( [id] => 13172415 [patent_doc_number] => 10102324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Reuse of extracted layout-dependent effects for circuit design using circuit stencils [patent_app_type] => utility [patent_app_number] => 15/442019 [patent_app_country] => US [patent_app_date] => 2017-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7468 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15442019 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/442019
Reuse of extracted layout-dependent effects for circuit design using circuit stencils Feb 23, 2017 Issued
Array ( [id] => 12122884 [patent_doc_number] => 20180006470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'MODULAR ENERGY STORAGE SYSTEMS AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 15/438743 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15438743 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/438743
Modular energy storage systems and related methods Feb 20, 2017 Issued
Array ( [id] => 14010053 [patent_doc_number] => 10223491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Integrated circuit design changes using through-silicon vias [patent_app_type] => utility [patent_app_number] => 15/431099 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10961 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431099 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/431099
Integrated circuit design changes using through-silicon vias Feb 12, 2017 Issued
Array ( [id] => 14458505 [patent_doc_number] => 10325218 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-18 [patent_title] => Constructing quantum process for quantum processors [patent_app_type] => utility [patent_app_number] => 15/419682 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/419682
Constructing quantum process for quantum processors Jan 29, 2017 Issued
Array ( [id] => 13306457 [patent_doc_number] => 20180204765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => MODIFIED SELF-ALIGNED QUADRUPLE PATTERNING (SAQP) PROCESSES USING CUT PATTERN MASKS TO FABRICATE INTEGRATED CIRCUIT (IC) CELLS WITH REDUCED AREA [patent_app_type] => utility [patent_app_number] => 15/408796 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408796 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408796
Modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area Jan 17, 2017 Issued
Array ( [id] => 14523965 [patent_doc_number] => 10339245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Timing exact design conversions from FPGA to ASIC [patent_app_type] => utility [patent_app_number] => 15/407242 [patent_app_country] => US [patent_app_date] => 2017-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 8092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15407242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/407242
Timing exact design conversions from FPGA to ASIC Jan 15, 2017 Issued
Array ( [id] => 17323158 [patent_doc_number] => 11214150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Method and arrangement for determining the state of charge of a battery pack [patent_app_type] => utility [patent_app_number] => 16/470740 [patent_app_country] => US [patent_app_date] => 2017-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7092 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16470740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/470740
Method and arrangement for determining the state of charge of a battery pack Jan 8, 2017 Issued
Array ( [id] => 15581733 [patent_doc_number] => 10581264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Adapter and charging control method [patent_app_type] => utility [patent_app_number] => 15/561713 [patent_app_country] => US [patent_app_date] => 2017-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 12808 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15561713 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/561713
Adapter and charging control method Jan 6, 2017 Issued
Array ( [id] => 13627613 [patent_doc_number] => 20180365358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => System and Method for the Design of Digital Hardware [patent_app_type] => utility [patent_app_number] => 16/061604 [patent_app_country] => US [patent_app_date] => 2016-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16061604 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/061604
System and method for the design of digital hardware Dec 8, 2016 Issued
Array ( [id] => 14703717 [patent_doc_number] => 10379600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Method of modifying a power mesh [patent_app_type] => utility [patent_app_number] => 15/369077 [patent_app_country] => US [patent_app_date] => 2016-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 6831 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15369077 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/369077
Method of modifying a power mesh Dec 4, 2016 Issued
Array ( [id] => 12755086 [patent_doc_number] => 20180143529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => METHOD OF FORMING PHOTOMASK [patent_app_type] => utility [patent_app_number] => 15/361007 [patent_app_country] => US [patent_app_date] => 2016-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15361007 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/361007
Method of forming photomask Nov 23, 2016 Issued
Array ( [id] => 14767209 [patent_doc_number] => 10395001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Multiple patterning layout decomposition considering complex coloring rules [patent_app_type] => utility [patent_app_number] => 15/359579 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 11623 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359579 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/359579
Multiple patterning layout decomposition considering complex coloring rules Nov 21, 2016 Issued
Array ( [id] => 14736403 [patent_doc_number] => 10387601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Methods to store dynamic layer content inside a design file [patent_app_type] => utility [patent_app_number] => 15/358888 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8091 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15358888 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/358888
Methods to store dynamic layer content inside a design file Nov 21, 2016 Issued
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