Vuthe Siek

Array ( [id] => 12756754 [patent_doc_number] => 20180144085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => SYSTEM DESIGN BASED ON UNIFIED CHIP SPECIFICATION [patent_app_type] => utility [patent_app_number] => 15/356543 [patent_app_country] => US [patent_app_date] => 2016-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12756760 [patent_doc_number] => 20180144087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => METHOD FOR EVALUATING FAILURE-IN-TIME [patent_app_type] => utility [patent_app_number] => 15/355410 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15355410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14490093 [patent_doc_number] => 10331837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-25 [patent_title] => Device graphics rendering for electronic designs [patent_app_type] => utility [patent_app_number] => 15/354894 [patent_app_country] => US [patent_app_date] => 2016-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 12945 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15354894 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12573312 [patent_doc_number] => 10020028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Data processing device [patent_app_type] => utility [patent_app_number] => 15/351600 [patent_app_country] => US [patent_app_date] => 2016-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 10617 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 681 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15351600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14614255 [patent_doc_number] => 10359825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Dynamic power measurement using formal [patent_app_type] => utility [patent_app_number] => 15/351644 [patent_app_country] => US [patent_app_date] => 2016-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13985 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15351644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11875622 [patent_doc_number] => 09747396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-29 [patent_title] => 'Driving pervasive commands using breakpoints in a hardware-accelerated simulation environment' [patent_app_type] => utility [patent_app_number] => 15/339314 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5172 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15339314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14150041 [patent_doc_number] => 10255402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-09 [patent_title] => System and method for instance snapping [patent_app_type] => utility [patent_app_number] => 15/277514 [patent_app_country] => US [patent_app_date] => 2016-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4278 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15277514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12180780 [patent_doc_number] => 20180039716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'METHODS AND SYSTEMS FOR MANAGING MEMORY BLOCKS OF SEMICONDUCTOR DEVICES IN EMBEDDED SYSTEMS' [patent_app_type] => utility [patent_app_number] => 15/276434 [patent_app_country] => US [patent_app_date] => 2016-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7107 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15276434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11531383 [patent_doc_number] => 20170091361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'SYSTEM AND PROCESS FOR SIMULATING THE BEHAVIORAL EFFECTS OF TIMING VIOLATIONS BETWEEN UNRELATED CLOCKS' [patent_app_type] => utility [patent_app_number] => 15/276035 [patent_app_country] => US [patent_app_date] => 2016-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15276035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13891995 [patent_doc_number] => 10198545 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-05 [patent_title] => Systems and methods for extraction of electrical specifications from prelayout simulations [patent_app_type] => utility [patent_app_number] => 15/276412 [patent_app_country] => US [patent_app_date] => 2016-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 6563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15276412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14286347 [patent_doc_number] => 20190140458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => CHARGING CONTROL METHOD, DEVICE, AND SYSTEM [patent_app_type] => utility [patent_app_number] => 16/097365 [patent_app_country] => US [patent_app_date] => 2016-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16097365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13200003 [patent_doc_number] => 10114920 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-30 [patent_title] => Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic [patent_app_type] => utility [patent_app_number] => 15/197142 [patent_app_country] => US [patent_app_date] => 2016-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9621 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15197142 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14150045 [patent_doc_number] => 10255404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-09 [patent_title] => Retiming with programmable power-up states [patent_app_type] => utility [patent_app_number] => 15/195843 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14010057 [patent_doc_number] => 10223493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-05 [patent_title] => Dynamic tag allocation for clock reconvergence pessimism removal [patent_app_type] => utility [patent_app_number] => 15/195517 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7232 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14331361 [patent_doc_number] => 10296701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-21 [patent_title] => Retiming with fixed power-up states [patent_app_type] => utility [patent_app_number] => 15/195837 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13753139 [patent_doc_number] => 10169517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Methods and systems for reducing congestion in very large scale integrated (VLSI) chip design [patent_app_type] => utility [patent_app_number] => 15/194845 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3937 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15194845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12892783 [patent_doc_number] => 20180189436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => METHOD FOR GENERATING AN ELECTRONIC CIRCUIT MODELLING SUBSTRATE COUPLING EFFECTS IN AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/739908 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15739908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13236105 [patent_doc_number] => 10131239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Charging station and method for charging a plug-in motor vehicle at a charging post [patent_app_type] => utility [patent_app_number] => 15/189024 [patent_app_country] => US [patent_app_date] => 2016-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1082 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15189024 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13236101 [patent_doc_number] => 10131237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Illuminated vehicle charging system [patent_app_type] => utility [patent_app_number] => 15/189637 [patent_app_country] => US [patent_app_date] => 2016-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 13863 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15189637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13160561 [patent_doc_number] => 10097016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => System and device for monitoring battery status [patent_app_type] => utility [patent_app_number] => 15/189259 [patent_app_country] => US [patent_app_date] => 2016-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7188 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15189259 [rel_patent_id] =>[rel_patent_doc_number] =>)