Search

Vuthe Siek

Examiner (ID: 4172, Phone: (571)272-1906 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2768, 2764, 2825, 2763, 2304, 2851
Total Applications
1837
Issued Applications
1629
Pending Applications
46
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11352677 [patent_doc_number] => 20160371417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'SIGNAL VIA POSITIONING IN A MULTI-LAYER CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 14/842862 [patent_app_country] => US [patent_app_date] => 2015-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6414 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14842862 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/842862
Signal via positioning in a multi-layer circuit board Sep 1, 2015 Issued
Array ( [id] => 10485921 [patent_doc_number] => 20150370940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'CLOCK-GATING PHASE ALGEBRA FOR CLOCK ANALYSIS' [patent_app_type] => utility [patent_app_number] => 14/840517 [patent_app_country] => US [patent_app_date] => 2015-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 18192 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14840517 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/840517
Clock-gating phase algebra for clock analysis Aug 30, 2015 Issued
Array ( [id] => 10732012 [patent_doc_number] => 20160078162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'CONDITIONAL PHASE ALGEBRA FOR CLOCK ANALYSIS' [patent_app_type] => utility [patent_app_number] => 14/840774 [patent_app_country] => US [patent_app_date] => 2015-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14771 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14840774 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/840774
Conditional phase algebra for clock analysis Aug 30, 2015 Issued
Array ( [id] => 10709135 [patent_doc_number] => 20160055282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/840422 [patent_app_country] => US [patent_app_date] => 2015-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 19200 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14840422 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/840422
Planar cavity MEMS and related structures, methods of manufacture and design structures Aug 30, 2015 Issued
Array ( [id] => 10462654 [patent_doc_number] => 20150347669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'ALTERATION OF A SIGNAL VALUE FOR AN FPGA AT RUNTIME' [patent_app_type] => utility [patent_app_number] => 14/823197 [patent_app_country] => US [patent_app_date] => 2015-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10711 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14823197 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/823197
Alteration of a signal value for an FPGA at runtime Aug 10, 2015 Issued
Array ( [id] => 11623678 [patent_doc_number] => 20170133867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'Battery Management System For Control Of Lithium Power Cells' [patent_app_type] => utility [patent_app_number] => 14/817051 [patent_app_country] => US [patent_app_date] => 2015-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10591 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14817051 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/817051
Battery management system for control of lithium power cells Aug 2, 2015 Issued
Array ( [id] => 10695967 [patent_doc_number] => 20160042113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'Method for power estimation for virtual prototyping models for semiconductors' [patent_app_type] => utility [patent_app_number] => 14/811401 [patent_app_country] => US [patent_app_date] => 2015-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4899 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14811401 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/811401
Method for power estimation for virtual prototyping models for semiconductors Jul 27, 2015 Abandoned
Array ( [id] => 13949049 [patent_doc_number] => 10210301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => System and method for implementing and validating star routing for power connections at chip level [patent_app_type] => utility [patent_app_number] => 14/806462 [patent_app_country] => US [patent_app_date] => 2015-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14806462 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/806462
System and method for implementing and validating star routing for power connections at chip level Jul 21, 2015 Issued
Array ( [id] => 10426733 [patent_doc_number] => 20150311744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'WIRELESS POWER FEEDING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/795109 [patent_app_country] => US [patent_app_date] => 2015-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7086 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14795109 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/795109
Wireless power feeding system Jul 8, 2015 Issued
Array ( [id] => 10425148 [patent_doc_number] => 20150310160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING HIGH DENSITY REGISTRATION MAPS FOR MASKS' [patent_app_type] => utility [patent_app_number] => 14/795576 [patent_app_country] => US [patent_app_date] => 2015-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4743 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14795576 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/795576
METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING HIGH DENSITY REGISTRATION MAPS FOR MASKS Jul 8, 2015 Abandoned
Array ( [id] => 15399861 [patent_doc_number] => 10540588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Deep neural network processing on hardware accelerators with stacked memory [patent_app_type] => utility [patent_app_number] => 14/754344 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 62 [patent_no_of_words] => 27432 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14754344 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/754344
Deep neural network processing on hardware accelerators with stacked memory Jun 28, 2015 Issued
Array ( [id] => 12393993 [patent_doc_number] => 09965580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Ranking combinations of mutants, test cases and random seeds in mutation testing [patent_app_type] => utility [patent_app_number] => 14/748309 [patent_app_country] => US [patent_app_date] => 2015-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7683 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14748309 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/748309
Ranking combinations of mutants, test cases and random seeds in mutation testing Jun 23, 2015 Issued
Array ( [id] => 13680323 [patent_doc_number] => 20160378898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => REDUCING THE LOAD ON THE BITLINES OF A ROM BITCELL ARRAY [patent_app_type] => utility [patent_app_number] => 14/748075 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14748075 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/748075
Reducing the load on the bitlines of a ROM bitcell array Jun 22, 2015 Issued
Array ( [id] => 15609881 [patent_doc_number] => 10586004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Method and apparatus for utilizing estimations for register retiming in a design compilation flow [patent_app_type] => utility [patent_app_number] => 14/746237 [patent_app_country] => US [patent_app_date] => 2015-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14746237 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/746237
Method and apparatus for utilizing estimations for register retiming in a design compilation flow Jun 21, 2015 Issued
Array ( [id] => 11352676 [patent_doc_number] => 20160371416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'SIGNAL VIA POSITIONING IN A MULTI-LAYER CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 14/745964 [patent_app_country] => US [patent_app_date] => 2015-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6838 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14745964 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/745964
Signal via positioning in a multi-layer circuit board Jun 21, 2015 Issued
Array ( [id] => 11352682 [patent_doc_number] => 20160371422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'METHOD FOR REUSING AND VERIFYING ELECTRONIC CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/744214 [patent_app_country] => US [patent_app_date] => 2015-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4081 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14744214 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/744214
Method for reusing and verifying electronic circuits Jun 18, 2015 Issued
Array ( [id] => 11095376 [patent_doc_number] => 20160292345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'Directed Self-Assembly-Aware Layout Decomposition For Multiple Patterning' [patent_app_type] => utility [patent_app_number] => 14/745231 [patent_app_country] => US [patent_app_date] => 2015-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7231 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14745231 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/745231
Directed self-assembly-aware layout decomposition for multiple patterning Jun 18, 2015 Issued
Array ( [id] => 11644299 [patent_doc_number] => 09665678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'Method and program for designing integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/744178 [patent_app_country] => US [patent_app_date] => 2015-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 11742 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14744178 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/744178
Method and program for designing integrated circuit Jun 18, 2015 Issued
Array ( [id] => 11354158 [patent_doc_number] => 20160372898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'OPTIMIZED HIGH CURRENT CONNECTOR PATTERN FOR PDB' [patent_app_type] => utility [patent_app_number] => 14/740923 [patent_app_country] => US [patent_app_date] => 2015-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14740923 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/740923
Optimized high current connector pattern for PDB Jun 15, 2015 Issued
Array ( [id] => 10383543 [patent_doc_number] => 20150268551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'PRODUCING RESIST LAYERS USING FINE SEGMENTATION' [patent_app_type] => utility [patent_app_number] => 14/734460 [patent_app_country] => US [patent_app_date] => 2015-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4058 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14734460 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/734460
Producing resist layers using fine segmentation Jun 8, 2015 Issued
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