Search

Vuthe Siek

Examiner (ID: 19021, Phone: (571)272-1906 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2763, 2304, 2768, 2851
Total Applications
1837
Issued Applications
1629
Pending Applications
46
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16928780 [patent_doc_number] => 11050279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Charge/discharge switch control circuits for batteries [patent_app_type] => utility [patent_app_number] => 16/745124 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16745124 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/745124
Charge/discharge switch control circuits for batteries Jan 15, 2020 Issued
Array ( [id] => 16980218 [patent_doc_number] => 20210224455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => Multi-Row Standard Cell Design Method in Hybrid Row Height System [patent_app_type] => utility [patent_app_number] => 16/744311 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/744311
Multi-row standard cell design method in hybrid row height system Jan 15, 2020 Issued
Array ( [id] => 17195170 [patent_doc_number] => 11163929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-02 [patent_title] => Generate clock network using inverting integrated clock gate [patent_app_type] => utility [patent_app_number] => 16/735672 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10705 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735672 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/735672
Generate clock network using inverting integrated clock gate Jan 5, 2020 Issued
Array ( [id] => 17121354 [patent_doc_number] => 11132490 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-28 [patent_title] => Using negative-edge integrated clock gate in clock network [patent_app_type] => utility [patent_app_number] => 16/735674 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11505 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735674 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/735674
Using negative-edge integrated clock gate in clock network Jan 5, 2020 Issued
Array ( [id] => 16895349 [patent_doc_number] => 11036905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-15 [patent_title] => Hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities [patent_app_type] => utility [patent_app_number] => 16/734669 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/734669
Hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities Jan 5, 2020 Issued
Array ( [id] => 16958208 [patent_doc_number] => 11062079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Method for compiling a quantum circuit on a quantum processor with trapped ions [patent_app_type] => utility [patent_app_number] => 16/727029 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4724 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727029 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727029
Method for compiling a quantum circuit on a quantum processor with trapped ions Dec 25, 2019 Issued
Array ( [id] => 16910642 [patent_doc_number] => 11042685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Method for developing a process for compiling a quantum circuit on a quantum processor and such process [patent_app_type] => utility [patent_app_number] => 16/727026 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727026 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727026
Method for developing a process for compiling a quantum circuit on a quantum processor and such process Dec 25, 2019 Issued
Array ( [id] => 16915015 [patent_doc_number] => 20210188107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => THREE-WAY TRANSFORMER FOR POWER CONVERSION IN ELECTRIC VEHICLES [patent_app_type] => utility [patent_app_number] => 16/724561 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724561 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724561
Three-way transformer for power conversion in electric vehicles Dec 22, 2019 Issued
Array ( [id] => 16758850 [patent_doc_number] => 10977401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-13 [patent_title] => Preparation of circuit designs for system-on-chip devices and implementation of circuitry using instances of a logical network-on-chip [patent_app_type] => utility [patent_app_number] => 16/724553 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724553 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724553
Preparation of circuit designs for system-on-chip devices and implementation of circuitry using instances of a logical network-on-chip Dec 22, 2019 Issued
Array ( [id] => 16895348 [patent_doc_number] => 11036904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Apparatus and method for ternary logic synthesis with modified Quine-McCluskey algorithm [patent_app_type] => utility [patent_app_number] => 16/714583 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5819 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714583 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714583
Apparatus and method for ternary logic synthesis with modified Quine-McCluskey algorithm Dec 12, 2019 Issued
Array ( [id] => 17001632 [patent_doc_number] => 11080444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-03 [patent_title] => Concurrent fault co-simulator [patent_app_type] => utility [patent_app_number] => 16/712938 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16712938 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/712938
Concurrent fault co-simulator Dec 11, 2019 Issued
Array ( [id] => 16911799 [patent_doc_number] => 11043851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Electronic device and its operation system [patent_app_type] => utility [patent_app_number] => 16/702852 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 15994 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702852 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/702852
Electronic device and its operation system Dec 3, 2019 Issued
Array ( [id] => 16779743 [patent_doc_number] => 20210116822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => CONTROL EQUIPMENT AND CONTROL METHOD OF STEPPER [patent_app_type] => utility [patent_app_number] => 16/691894 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16691894 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/691894
Control equipment and control method of stepper Nov 21, 2019 Issued
Array ( [id] => 16773050 [patent_doc_number] => 10984161 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-20 [patent_title] => System, method, and computer program product for sequential equivalence checking in formal verification [patent_app_type] => utility [patent_app_number] => 16/689410 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7987 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689410
System, method, and computer program product for sequential equivalence checking in formal verification Nov 19, 2019 Issued
Array ( [id] => 15654601 [patent_doc_number] => 20200089831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => AUTOMATED METHOD FOR INTEGRATED ANALYSIS OF BACK END OF THE LINE YIELD, LINE RESISTANCE/CAPACITANCE AND PROCESS PERFORMANCE [patent_app_type] => utility [patent_app_number] => 16/684919 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684919 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684919
Automated method for integrated analysis of back end of the line yield, line resistance/capacitance and process performance Nov 14, 2019 Issued
Array ( [id] => 16823615 [patent_doc_number] => 20210138908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => VEHICLE INCLUDING REMOTE TERMINALS CONNECTED TO BATTERY SO AS TO PREVENT ELECTRONIC TAMPERING [patent_app_type] => utility [patent_app_number] => 16/682053 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682053 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682053
Vehicle including remote terminals connected to battery so as to prevent electronic tampering Nov 12, 2019 Issued
Array ( [id] => 17468644 [patent_doc_number] => 11275119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Methods and system for a battery [patent_app_type] => utility [patent_app_number] => 16/670650 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2969 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670650 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670650
Methods and system for a battery Oct 30, 2019 Issued
Array ( [id] => 16535561 [patent_doc_number] => 10878162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Metal with buried power for increased IC device density [patent_app_type] => utility [patent_app_number] => 16/669338 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 40 [patent_no_of_words] => 15096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669338 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/669338
Metal with buried power for increased IC device density Oct 29, 2019 Issued
Array ( [id] => 16292483 [patent_doc_number] => 10769335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-08 [patent_title] => System and method for graph based verification of electronic circuit design [patent_app_type] => utility [patent_app_number] => 16/667748 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667748 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667748
System and method for graph based verification of electronic circuit design Oct 28, 2019 Issued
Array ( [id] => 16121587 [patent_doc_number] => 20200212816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => ON-BOARD CHARGING/DISCHARGING SYSTEM AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/666168 [patent_app_country] => US [patent_app_date] => 2019-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 701 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16666168 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/666168
On-board charging/discharging system and control method thereof Oct 27, 2019 Issued
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