Vuthe Siek

Array ( [id] => 10300260 [patent_doc_number] => 20150185260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'POWER ADAPTER DETECTION' [patent_app_type] => utility [patent_app_number] => 14/125462 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6467 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14125462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10009754 [patent_doc_number] => 09053276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Methodology for nanoscale technology based mixed-signal system design' [patent_app_type] => utility [patent_app_number] => 13/928786 [patent_app_country] => US [patent_app_date] => 2013-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 10443 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13928786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10824971 [patent_doc_number] => 20160171136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'METHOD FOR AUTOMATED ASSISTANCE TO DESIGN NONLINEAR ANALOG CIRCUIT WITH TRANSIENT SOLVER' [patent_app_type] => utility [patent_app_number] => 14/410308 [patent_app_country] => US [patent_app_date] => 2013-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 23567 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14410308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10977224 [patent_doc_number] => 20140380259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'LAYOUT MIGRATION WITH HIERARCHICAL SCALE AND BIAS METHOD' [patent_app_type] => utility [patent_app_number] => 13/923256 [patent_app_country] => US [patent_app_date] => 2013-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9578 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13923256 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9444358 [patent_doc_number] => 08713494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Synthesizing VHDL multiple wait FSMS into RT level FSMS by preprocessing' [patent_app_type] => utility [patent_app_number] => 13/917638 [patent_app_country] => US [patent_app_date] => 2013-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2621 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13917638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9176502 [patent_doc_number] => 20130318487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'Programmable Circuit Characteristics Analysis' [patent_app_type] => utility [patent_app_number] => 13/901506 [patent_app_country] => US [patent_app_date] => 2013-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13901506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9879115 [patent_doc_number] => 08966411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Standardized topographical arrangements for template regions that orient self-assembly' [patent_app_type] => utility [patent_app_number] => 13/899936 [patent_app_country] => US [patent_app_date] => 2013-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 50 [patent_no_of_words] => 17678 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13899936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9065143 [patent_doc_number] => 20130256898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'Optimizing Layout of Irregular Structures in Regular Layout Context' [patent_app_type] => utility [patent_app_number] => 13/898155 [patent_app_country] => US [patent_app_date] => 2013-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 16215 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13898155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9044355 [patent_doc_number] => 20130246993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'METHOD FOR ASSIGNING TERMINAL OF SEMICONDUCTOR PACKAGE, APPARATUS, AND SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/889746 [patent_app_country] => US [patent_app_date] => 2013-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8503 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13889746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9163681 [patent_doc_number] => 20130311958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'PATTERN SELECTION FOR FULL-CHIP SOURCE AND MASK OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 13/888816 [patent_app_country] => US [patent_app_date] => 2013-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13888816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10212526 [patent_doc_number] => 20150097518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'HYBRID BATTERY CONTROL' [patent_app_type] => utility [patent_app_number] => 14/398706 [patent_app_country] => US [patent_app_date] => 2013-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7204 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14398706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9992782 [patent_doc_number] => 09038003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Method and system for critical dimension uniformity using charged particle beam lithography' [patent_app_type] => utility [patent_app_number] => 13/862476 [patent_app_country] => US [patent_app_date] => 2013-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 10280 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13862476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10210869 [patent_doc_number] => 20150095861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'METHOD FOR PRODUCING A DPA-RESISTANT LOGIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/396500 [patent_app_country] => US [patent_app_date] => 2013-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4699 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14396500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10310009 [patent_doc_number] => 20150195010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'INFORMATION PROVISION SYSTEM AND INFORMATION PROVISION METHOD' [patent_app_type] => utility [patent_app_number] => 14/404843 [patent_app_country] => US [patent_app_date] => 2013-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3656 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14404843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9774617 [patent_doc_number] => 20140298280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'REDUCING RUNTIME AND MEMORY REQUIREMENTS OF STATIC TIMING ANALYSIS' [patent_app_type] => utility [patent_app_number] => 13/855226 [patent_app_country] => US [patent_app_date] => 2013-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13855226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9774615 [patent_doc_number] => 20140298278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'GRAPHICAL METHOD AND PRODUCT TO ASSIGN PHYSICAL ATTRIBUTES TO ENTITIES IN A HIGH LEVEL DESCRIPTIVE LANGUAGE USED FOR VLSI CHIP DESIGN' [patent_app_type] => utility [patent_app_number] => 13/855416 [patent_app_country] => US [patent_app_date] => 2013-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5301 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13855416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10930244 [patent_doc_number] => 20140333265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'DEGRADATION STATE ESTIMATING METHOD AND DEGRADATION STATE ESTIMATING APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/117491 [patent_app_country] => US [patent_app_date] => 2013-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14823 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14117491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9766028 [patent_doc_number] => 08850376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Method, device, and a computer-readable recording medium having stored program for information processing for noise suppression design check' [patent_app_type] => utility [patent_app_number] => 13/849706 [patent_app_country] => US [patent_app_date] => 2013-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7250 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13849706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9006386 [patent_doc_number] => 20130227511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'METHOD FOR REPEATED BLOCK MODIFICATION FOR CHIP ROUTING' [patent_app_type] => utility [patent_app_number] => 13/849995 [patent_app_country] => US [patent_app_date] => 2013-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13849995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12249370 [patent_doc_number] => 09922146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Tool apparatus, method and computer program for designing an integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/778107 [patent_app_country] => US [patent_app_date] => 2013-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6325 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14778107 [rel_patent_id] =>[rel_patent_doc_number] =>)