Vuthe Siek

Array ( [id] => 16046587 [patent_doc_number] => 10685167 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-16 [patent_title] => System, method, and computer program product for displaying bump layout for manufacturing variations [patent_app_type] => utility [patent_app_number] => 16/147832 [patent_app_country] => US [patent_app_date] => 2018-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 6821 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16279229 [patent_doc_number] => 10762260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-01 [patent_title] => Methods, systems, and computer program product for implementing an electronic design with optimization maps [patent_app_type] => utility [patent_app_number] => 16/147764 [patent_app_country] => US [patent_app_date] => 2018-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16409080 [patent_doc_number] => 10817635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Multiple patterning method for semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/133110 [patent_app_country] => US [patent_app_date] => 2018-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 7212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16133110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17557215 [patent_doc_number] => 11313910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Anomaly detection system and anomaly detection method for a secondary battery [patent_app_type] => utility [patent_app_number] => 16/645980 [patent_app_country] => US [patent_app_date] => 2018-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6345 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16645980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15756877 [patent_doc_number] => 10620547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Method for correcting a mask layout and method of fabricating a semiconductor device using the same [patent_app_type] => utility [patent_app_number] => 16/030061 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5659 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16232976 [patent_doc_number] => 10740528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Method of generating a 3D circuit layout from a 2D circuit layout [patent_app_type] => utility [patent_app_number] => 16/027545 [patent_app_country] => US [patent_app_date] => 2018-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5476 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16027545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14471817 [patent_doc_number] => 20190187552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => OPTICAL PROXIMITY CORRECTION (OPC) METHOD AND METHOD OF MANUFACTURING MASK BY USING THE OPC METHOD [patent_app_type] => utility [patent_app_number] => 16/027644 [patent_app_country] => US [patent_app_date] => 2018-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16027644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13934007 [patent_doc_number] => 20190050519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => DIE INTERFACE ENABLING 2.5 D DEVICE-LEVEL STATIC TIMING ANALYSIS [patent_app_type] => utility [patent_app_number] => 16/026950 [patent_app_country] => US [patent_app_date] => 2018-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16026950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16478601 [patent_doc_number] => 10853550 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-01 [patent_title] => Sampling selection for enhanced high yield estimation in circuit designs [patent_app_type] => utility [patent_app_number] => 16/027231 [patent_app_country] => US [patent_app_date] => 2018-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12076 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16027231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17470531 [patent_doc_number] => 11277016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Charging device, method for charging a mobile terminal, control unit and motor vehicle [patent_app_type] => utility [patent_app_number] => 16/625140 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 9001 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16625140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13499259 [patent_doc_number] => 20180301172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => DATA PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 16/010770 [patent_app_country] => US [patent_app_date] => 2018-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16010770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15272301 [patent_doc_number] => 20190384885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => INTEGRATED CIRCUIT (IC) DESIGN SYSTEMS AND METHODS USING SINGLE-PIN IMAGINARY DEVICES [patent_app_type] => utility [patent_app_number] => 16/008176 [patent_app_country] => US [patent_app_date] => 2018-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15258231 [patent_doc_number] => 20190377849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => GENERATIVE ADVERSARIAL NETWORKS FOR GENERATING PHYSICAL DESIGN LAYOUT PATTERNS [patent_app_type] => utility [patent_app_number] => 16/005999 [patent_app_country] => US [patent_app_date] => 2018-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16005999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13611591 [patent_doc_number] => 20180357345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => APPLICATION-SPECIFIC PROCESSOR GENERATION FROM GENERAL PURPOSE PROCESSORS [patent_app_type] => utility [patent_app_number] => 16/006495 [patent_app_country] => US [patent_app_date] => 2018-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16006495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15758541 [patent_doc_number] => 10621387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => On-die decoupling capacitor area optimization [patent_app_type] => utility [patent_app_number] => 15/993206 [patent_app_country] => US [patent_app_date] => 2018-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5714 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14901961 [patent_doc_number] => 20190294746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => MODEL-BUILDING METHOD FOR BUILDING TOP INTERFACE LOGIC MODEL [patent_app_type] => utility [patent_app_number] => 15/992213 [patent_app_country] => US [patent_app_date] => 2018-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15992213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13434901 [patent_doc_number] => 20180268993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => WIRELESS CHARGING DEVICE FOR AN ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 15/982452 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13403959 [patent_doc_number] => 20180253522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => Cell Layout and Structure [patent_app_type] => utility [patent_app_number] => 15/971646 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16514759 [patent_doc_number] => 20200394017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => FAST BINARY COUNTERS BASED ON SYMMETRIC STACKING AND METHODS FOR SAME [patent_app_type] => utility [patent_app_number] => 16/610761 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16610761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15855459 [patent_doc_number] => 10643017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Rule checking for multiple patterning technology [patent_app_type] => utility [patent_app_number] => 15/962822 [patent_app_country] => US [patent_app_date] => 2018-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 7315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15962822 [rel_patent_id] =>[rel_patent_doc_number] =>)