
Wael M. Fahmy
Supervisory Patent Examiner (ID: 2197, Phone: (571)272-1705 , Office: P/2814 )
| Most Active Art Unit | 2508 |
| Art Unit(s) | 2508, 2811, 2823, 2814, 1931 |
| Total Applications | 712 |
| Issued Applications | 535 |
| Pending Applications | 22 |
| Abandoned Applications | 155 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20436020
[patent_doc_number] => 12507527
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-23
[patent_title] => Transparent display device and method of manufacturing a transparent display device
[patent_app_type] => utility
[patent_app_number] => 18/755721
[patent_app_country] => US
[patent_app_date] => 2024-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 9985
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755721
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/755721 | Transparent display device and method of manufacturing a transparent display device | Jun 26, 2024 | Issued |
Array
(
[id] => 20339038
[patent_doc_number] => 20250343158
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-06
[patent_title] => Semiconductor Device and Method of Forming C2W Package with EMI Shielding
[patent_app_type] => utility
[patent_app_number] => 18/651785
[patent_app_country] => US
[patent_app_date] => 2024-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 937
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651785
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/651785 | Semiconductor Device and Method of Forming C2W Package with EMI Shielding | Apr 30, 2024 | Pending |
Array
(
[id] => 20066047
[patent_doc_number] => 20250204269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-19
[patent_title] => NEUROMORPHIC DEVICES OF HEUSLER ALLOY BASED SPIN-TRANSFER-TORQUE MAGNETIC TUNNEL JUNCTIONS
[patent_app_type] => utility
[patent_app_number] => 18/541040
[patent_app_country] => US
[patent_app_date] => 2023-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10092
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18541040
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/541040 | NEUROMORPHIC DEVICES OF HEUSLER ALLOY BASED SPIN-TRANSFER-TORQUE MAGNETIC TUNNEL JUNCTIONS | Dec 14, 2023 | Pending |
Array
(
[id] => 20217683
[patent_doc_number] => 12414352
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-09
[patent_title] => Two-dimensional vertical fins
[patent_app_type] => utility
[patent_app_number] => 18/485842
[patent_app_country] => US
[patent_app_date] => 2023-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 1121
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18485842
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/485842 | Two-dimensional vertical fins | Oct 11, 2023 | Issued |
Array
(
[id] => 20483930
[patent_doc_number] => 12532408
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-20
[patent_title] => Electronic device and package structure
[patent_app_type] => utility
[patent_app_number] => 17/981338
[patent_app_country] => US
[patent_app_date] => 2022-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2180
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17981338
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/981338 | Electronic device and package structure | Nov 3, 2022 | Issued |
Array
(
[id] => 20496594
[patent_doc_number] => 12538483
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-27
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/896934
[patent_app_country] => US
[patent_app_date] => 2022-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 31
[patent_no_of_words] => 3544
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 265
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896934
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/896934 | Semiconductor device | Aug 25, 2022 | Issued |
Array
(
[id] => 20004639
[patent_doc_number] => 20250142861
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-01
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/681865
[patent_app_country] => US
[patent_app_date] => 2022-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 992
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18681865
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/681865 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | Aug 11, 2022 | Pending |
Array
(
[id] => 18009245
[patent_doc_number] => 20220368012
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => INTEGRATED PATCH ANTENNA HAVING AN INSULATING SUBSTRATE WITH AN ANTENNA CAVITY AND A HIGH-K DIELECTRIC
[patent_app_type] => utility
[patent_app_number] => 17/871271
[patent_app_country] => US
[patent_app_date] => 2022-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12960
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871271
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/871271 | INTEGRATED PATCH ANTENNA HAVING AN INSULATING SUBSTRATE WITH AN ANTENNA CAVITY AND A HIGH-K DIELECTRIC | Jul 21, 2022 | Pending |
Array
(
[id] => 20361788
[patent_doc_number] => 12477806
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-18
[patent_title] => Semiconductor device having buried gate structure
[patent_app_type] => utility
[patent_app_number] => 17/861282
[patent_app_country] => US
[patent_app_date] => 2022-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 3792
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861282
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/861282 | Semiconductor device having buried gate structure | Jul 10, 2022 | Issued |
Array
(
[id] => 17949264
[patent_doc_number] => 20220336283
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => WAFER ADAPTORS, INCLUDING SYSTEMS AND METHODS, FOR ADAPTING DIFFERENT SIZED WAFERS
[patent_app_type] => utility
[patent_app_number] => 17/722416
[patent_app_country] => US
[patent_app_date] => 2022-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11901
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722416
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/722416 | WAFER ADAPTORS, INCLUDING SYSTEMS AND METHODS, FOR ADAPTING DIFFERENT SIZED WAFERS | Apr 17, 2022 | Pending |
Array
(
[id] => 19646265
[patent_doc_number] => 20240420785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => MAGNETIC DOMAIN WALL MOTION ELEMENT, MAGNETIC RECORDING ARRAY, AND MAGNETIC MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/702662
[patent_app_country] => US
[patent_app_date] => 2021-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10873
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18702662
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/702662 | MAGNETIC DOMAIN WALL MOTION ELEMENT, MAGNETIC RECORDING ARRAY, AND MAGNETIC MEMORY | Oct 20, 2021 | Pending |
Array
(
[id] => 18068385
[patent_doc_number] => 20220399473
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-15
[patent_title] => METHOD OF MANUFACTURING DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/777136
[patent_app_country] => US
[patent_app_date] => 2020-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25126
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17777136
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/777136 | Method of manufacturing display device | May 26, 2020 | Issued |
Array
(
[id] => 16119775
[patent_doc_number] => 20200211910
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-02
[patent_title] => MULTILAYER MOS DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/722406
[patent_app_country] => US
[patent_app_date] => 2019-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5262
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16722406
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/722406 | MULTILAYER MOS DEVICE AND METHOD FOR MANUFACTURING THE SAME | Dec 19, 2019 | Abandoned |
Array
(
[id] => 11732907
[patent_doc_number] => 20170194350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-06
[patent_title] => 'LOW-NOISE MOS TRANSISTORS AND CORRESPONDING CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 15/137540
[patent_app_country] => US
[patent_app_date] => 2016-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1714
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15137540
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/137540 | LOW-NOISE MOS TRANSISTORS AND CORRESPONDING CIRCUIT | Apr 24, 2016 | Abandoned |
Array
(
[id] => 11024865
[patent_doc_number] => 20160221820
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-08-04
[patent_title] => 'SEMICONDUCTOR PACKAGE USING A POLYMER SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 15/009012
[patent_app_country] => US
[patent_app_date] => 2016-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4513
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15009012
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/009012 | SEMICONDUCTOR PACKAGE USING A POLYMER SUBSTRATE | Jan 27, 2016 | Abandoned |
Array
(
[id] => 13695563
[patent_doc_number] => 20170358736
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-14
[patent_title] => METHOD FOR MANUFACTURING A HALL SENSOR
[patent_app_type] => utility
[patent_app_number] => 15/546994
[patent_app_country] => US
[patent_app_date] => 2016-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2771
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15546994
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/546994 | METHOD FOR MANUFACTURING A HALL SENSOR | Jan 12, 2016 | Abandoned |
Array
(
[id] => 9770546
[patent_doc_number] => 20140294208
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-10-02
[patent_title] => 'LIGHT-BASED DETECTION FOR ACOUSTIC APPLICATIONS'
[patent_app_type] => utility
[patent_app_number] => 14/225339
[patent_app_country] => US
[patent_app_date] => 2014-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 14326
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14225339
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/225339 | LIGHT-BASED DETECTION FOR ACOUSTIC APPLICATIONS | Mar 24, 2014 | Abandoned |
Array
(
[id] => 9269227
[patent_doc_number] => 20140024144
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-23
[patent_title] => 'INTEGRATED CIRCUIT DIE AND METHOD OF MAKING'
[patent_app_type] => utility
[patent_app_number] => 14/039055
[patent_app_country] => US
[patent_app_date] => 2013-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3794
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14039055
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/039055 | INTEGRATED CIRCUIT DIE AND METHOD OF MAKING | Sep 26, 2013 | Abandoned |
Array
(
[id] => 9104713
[patent_doc_number] => 20130277844
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-24
[patent_title] => 'THROUGH VIA PROCESS'
[patent_app_type] => utility
[patent_app_number] => 13/921032
[patent_app_country] => US
[patent_app_date] => 2013-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2071
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13921032
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/921032 | THROUGH VIA PROCESS | Jun 17, 2013 | Abandoned |
Array
(
[id] => 9728737
[patent_doc_number] => 20140264444
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'STRESS-ENHANCING SELECTIVE EPITAXIAL DEPOSITION OF EMBEDDED SOURCE AND DRAIN REGIONS'
[patent_app_type] => utility
[patent_app_number] => 13/798467
[patent_app_country] => US
[patent_app_date] => 2013-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 4388
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13798467
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/798467 | STRESS-ENHANCING SELECTIVE EPITAXIAL DEPOSITION OF EMBEDDED SOURCE AND DRAIN REGIONS | Mar 12, 2013 |