Wael M. Fahmy

Array ( [id] => 3557424 [patent_doc_number] => 05574295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Dielectrically isolated SiC mosfet' [patent_app_type] => 1 [patent_app_number] => 8/512892 [patent_app_country] => US [patent_app_date] => 1995-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 3305 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574295.pdf [firstpage_image] =>[orig_patent_app_number] => 512892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3698490 [patent_doc_number] => 05661325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'SRAM structure' [patent_app_type] => 1 [patent_app_number] => 8/508986 [patent_app_country] => US [patent_app_date] => 1995-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 6793 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661325.pdf [firstpage_image] =>[orig_patent_app_number] => 508986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3662796 [patent_doc_number] => 05591994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Compound semiconductor field effect transistor having a controlled diffusion profile of impurity elements' [patent_app_type] => 1 [patent_app_number] => 8/507638 [patent_app_country] => US [patent_app_date] => 1995-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 11003 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/591/05591994.pdf [firstpage_image] =>[orig_patent_app_number] => 507638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3932863 [patent_doc_number] => 05877518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Semiconductor device and inverter apparatus using the semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/504422 [patent_app_country] => US [patent_app_date] => 1995-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 6113 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877518.pdf [firstpage_image] =>[orig_patent_app_number] => 504422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3732464 [patent_doc_number] => 05652456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Semiconductor structure containing multiple optimized well regions' [patent_app_type] => 1 [patent_app_number] => 8/503962 [patent_app_country] => US [patent_app_date] => 1995-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 5350 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652456.pdf [firstpage_image] =>[orig_patent_app_number] => 503962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4062272 [patent_doc_number] => 05864169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Semiconductor device including plated heat sink and airbridge for heat dissipation' [patent_app_type] => 1 [patent_app_number] => 8/503952 [patent_app_country] => US [patent_app_date] => 1995-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 55 [patent_no_of_words] => 21323 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864169.pdf [firstpage_image] =>[orig_patent_app_number] => 503952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3732900 [patent_doc_number] => 05670804 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'PN-junction gate FET' [patent_app_type] => 1 [patent_app_number] => 8/501956 [patent_app_country] => US [patent_app_date] => 1995-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/670/05670804.pdf [firstpage_image] =>[orig_patent_app_number] => 501956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3559122 [patent_doc_number] => 05543643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Combined JFET and MOS transistor device, circuit' [patent_app_type] => 1 [patent_app_number] => 8/502566 [patent_app_country] => US [patent_app_date] => 1995-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2790 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/543/05543643.pdf [firstpage_image] =>[orig_patent_app_number] => 502566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3954716 [patent_doc_number] => 05955775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Structure of complementary bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/501634 [patent_app_country] => US [patent_app_date] => 1995-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4984 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/955/05955775.pdf [firstpage_image] =>[orig_patent_app_number] => 501634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3557593 [patent_doc_number] => 05574306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Lateral bipolar transistor and FET' [patent_app_type] => 1 [patent_app_number] => 8/500470 [patent_app_country] => US [patent_app_date] => 1995-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 1931 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574306.pdf [firstpage_image] =>[orig_patent_app_number] => 500470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3638169 [patent_doc_number] => 05610430 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Semiconductor device having reduced gate overlapping capacitance' [patent_app_type] => 1 [patent_app_number] => 8/494384 [patent_app_country] => US [patent_app_date] => 1995-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 92 [patent_no_of_words] => 17958 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610430.pdf [firstpage_image] =>[orig_patent_app_number] => 494384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3595927 [patent_doc_number] => 05521412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Low and high minority carrier lifetime layers in a single semiconductor structure' [patent_app_type] => 1 [patent_app_number] => 8/494858 [patent_app_country] => US [patent_app_date] => 1995-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 1245 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521412.pdf [firstpage_image] =>[orig_patent_app_number] => 494858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3586198 [patent_doc_number] => 05581114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Self-aligned polysilicon base contact in a bipolar junction transistor' [patent_app_type] => 1 [patent_app_number] => 8/482164 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4498 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581114.pdf [firstpage_image] =>[orig_patent_app_number] => 482164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3864448 [patent_doc_number] => 05793065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Insulated-gate thyristor' [patent_app_type] => 1 [patent_app_number] => 8/483325 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 159 [patent_figures_cnt] => 261 [patent_no_of_words] => 40727 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793065.pdf [firstpage_image] =>[orig_patent_app_number] => 483325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3594564 [patent_doc_number] => 05567966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Local thinning of channel region for ultra-thin film SOI MOSFET with elevated source/drain' [patent_app_type] => 1 [patent_app_number] => 8/478310 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 1323 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/567/05567966.pdf [firstpage_image] =>[orig_patent_app_number] => 478310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4016695 [patent_doc_number] => 05962870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Insulated gate field effect semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/467984 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 38 [patent_no_of_words] => 8888 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/962/05962870.pdf [firstpage_image] =>[orig_patent_app_number] => 467984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3885555 [patent_doc_number] => 05798550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Vertical type semiconductor device and gate structure' [patent_app_type] => 1 [patent_app_number] => 8/469622 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 46 [patent_no_of_words] => 9390 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798550.pdf [firstpage_image] =>[orig_patent_app_number] => 469622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3579562 [patent_doc_number] => 05523594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/464464 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3815 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/523/05523594.pdf [firstpage_image] =>[orig_patent_app_number] => 464464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3602608 [patent_doc_number] => 05559348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Semiconductor device having insulated gate bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/460942 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 6885 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559348.pdf [firstpage_image] =>[orig_patent_app_number] => 460942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3624389 [patent_doc_number] => 05614739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'HIGFET and method' [patent_app_type] => 1 [patent_app_number] => 8/459854 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1446 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/614/05614739.pdf [firstpage_image] =>[orig_patent_app_number] => 459854 [rel_patent_id] =>[rel_patent_doc_number] =>)