Search

Walter A. Moore

Examiner (ID: 5263, Phone: (571)270-7372 , Office: P/1793 )

Most Active Art Unit
1793
Art Unit(s)
1783, 1793, CQIC, 1794, 3619, 1789
Total Applications
541
Issued Applications
122
Pending Applications
5
Abandoned Applications
413

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15807525 [patent_doc_number] => 20200126905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => MEMORY ARRAY STRUCTURE AND METHOD OF FABRICATING THEREOF [patent_app_type] => utility [patent_app_number] => 16/723323 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723323 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/723323
Method of fabricating a memory device having multiple metal interconnect lines Dec 19, 2019 Issued
Array ( [id] => 16272283 [patent_doc_number] => 20200273771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/720131 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16720131 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/720131
Semiconductor package Dec 18, 2019 Issued
Array ( [id] => 16904872 [patent_doc_number] => 20210183788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => POWER DEVICE INCLUDING METAL LAYER [patent_app_type] => utility [patent_app_number] => 16/714249 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714249 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714249
Power device including metal layer Dec 12, 2019 Issued
Array ( [id] => 15776061 [patent_doc_number] => 20200119048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING STANDARD CELLS [patent_app_type] => utility [patent_app_number] => 16/712356 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16712356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/712356
Semiconductor device including standard cells having different cell height Dec 11, 2019 Issued
Array ( [id] => 17032823 [patent_doc_number] => 11094641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Fan-out package having a main die and a dummy die [patent_app_type] => utility [patent_app_number] => 16/705308 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 36 [patent_no_of_words] => 8622 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705308 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/705308
Fan-out package having a main die and a dummy die Dec 5, 2019 Issued
Array ( [id] => 16888984 [patent_doc_number] => 20210175181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => INTEGRATED DEVICE WITH ELECTROMAGNETIC SHIELD [patent_app_type] => utility [patent_app_number] => 16/706167 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16706167 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/706167
Integrated device with electromagnetic shield Dec 5, 2019 Issued
Array ( [id] => 17803311 [patent_doc_number] => 11417624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Electronic device having supporting resin and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/704961 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 18470 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704961 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704961
Electronic device having supporting resin and manufacturing method thereof Dec 4, 2019 Issued
Array ( [id] => 16738972 [patent_doc_number] => 10964638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Vertical memory device including common source line structure [patent_app_type] => utility [patent_app_number] => 16/704499 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 18508 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704499 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704499
Vertical memory device including common source line structure Dec 4, 2019 Issued
Array ( [id] => 16765519 [patent_doc_number] => 20210111101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => Semiconductor Structure Having Through-Substrate Via (TSV) in Porous Semiconductor Region [patent_app_type] => utility [patent_app_number] => 16/703367 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703367 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703367
Semiconductor structure having through-substrate via (TSV) in porous semiconductor region Dec 3, 2019 Issued
Array ( [id] => 16609573 [patent_doc_number] => 10910589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Flexible display apparatus having polarization structure extending up to bending part [patent_app_type] => utility [patent_app_number] => 16/688293 [patent_app_country] => US [patent_app_date] => 2019-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12876 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16688293 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/688293
Flexible display apparatus having polarization structure extending up to bending part Nov 18, 2019 Issued
Array ( [id] => 16536730 [patent_doc_number] => 10879345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Semiconductor device including a plurality of electrodes and supporters [patent_app_type] => utility [patent_app_number] => 16/679871 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16679871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/679871
Semiconductor device including a plurality of electrodes and supporters Nov 10, 2019 Issued
Array ( [id] => 15598475 [patent_doc_number] => 20200075772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => NANOSHEET FET INCLUDING ALL-AROUND SOURCE/DRAIN CONTACT [patent_app_type] => utility [patent_app_number] => 16/674090 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16674090 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/674090
Nanosheet FET including encapsulated all-around source/drain contact Nov 4, 2019 Issued
Array ( [id] => 15907235 [patent_doc_number] => 20200153138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => Semiconductor Power Module and Method for Producing a Semiconductor Power Module [patent_app_type] => utility [patent_app_number] => 16/673401 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16673401 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/673401
Semiconductor power module and method for producing a semiconductor power module Nov 3, 2019 Issued
Array ( [id] => 16812180 [patent_doc_number] => 20210134735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => STRESS MITIGATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/670564 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8800 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670564 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670564
Stress mitigation structure Oct 30, 2019 Issued
Array ( [id] => 16765504 [patent_doc_number] => 20210111086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => SELECTIVE MOLDING FOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/597915 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597915 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/597915
Selective molding for integrated circuit Oct 9, 2019 Issued
Array ( [id] => 17270489 [patent_doc_number] => 11195920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Semiconductor structure having porous semiconductor segment for RF devices and bulk semiconductor region for non-RF devices [patent_app_type] => utility [patent_app_number] => 16/598803 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5249 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598803 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598803
Semiconductor structure having porous semiconductor segment for RF devices and bulk semiconductor region for non-RF devices Oct 9, 2019 Issued
Array ( [id] => 16765437 [patent_doc_number] => 20210111019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => Semiconductor Structure Having Porous Semiconductor Layer for RF Devices [patent_app_type] => utility [patent_app_number] => 16/597779 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597779 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/597779
Semiconductor structure having porous semiconductor layer for RF devices Oct 8, 2019 Issued
Array ( [id] => 17395857 [patent_doc_number] => 11244881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Package terminal cavities [patent_app_type] => utility [patent_app_number] => 16/588544 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3543 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588544 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/588544
Package terminal cavities Sep 29, 2019 Issued
Array ( [id] => 15443011 [patent_doc_number] => 20200035689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => EIGHT-TRANSISTOR STATIC RANDOM ACCESS MEMORY, LAYOUT THEREOF, AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/588828 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588828 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/588828
Eight-transistor static random access memory, layout thereof, and method for manufacturing the same Sep 29, 2019 Issued
Array ( [id] => 17196011 [patent_doc_number] => 11164776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Metallic interconnect structure [patent_app_type] => utility [patent_app_number] => 16/588057 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4905 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588057 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/588057
Metallic interconnect structure Sep 29, 2019 Issued
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