Search

Walter H. Swanson

Examiner (ID: 15645, Phone: (571)270-3322 , Office: P/2823 )

Most Active Art Unit
2823
Art Unit(s)
2809, 4137, 2815, 2823
Total Applications
1133
Issued Applications
895
Pending Applications
48
Abandoned Applications
217

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19314478 [patent_doc_number] => 12040304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Semiconductor package and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 18/061008 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10674 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18061008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/061008
Semiconductor package and method of fabricating the same Dec 1, 2022 Issued
Array ( [id] => 18423907 [patent_doc_number] => 20230178371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => METHOD AND APPARATUS FOR HARD MASK DEPOSITION [patent_app_type] => utility [patent_app_number] => 18/061260 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18061260 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/061260
Method and apparatus for hard mask deposition Dec 1, 2022 Issued
Array ( [id] => 18323764 [patent_doc_number] => 20230121892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => Ferroelectric Capacitor, Ferroelectric Field Effect Transistor, and Method Used in Forming an Electronic Component Comprising Conductive Material and Ferroelectric Material [patent_app_type] => utility [patent_app_number] => 18/072546 [patent_app_country] => US [patent_app_date] => 2022-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18072546 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/072546
Ferroelectric capacitors Nov 29, 2022 Issued
Array ( [id] => 20389368 [patent_doc_number] => 12489103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Semiconductor module [patent_app_type] => utility [patent_app_number] => 18/057223 [patent_app_country] => US [patent_app_date] => 2022-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4315 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18057223 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/057223
Semiconductor module Nov 19, 2022 Issued
Array ( [id] => 18555189 [patent_doc_number] => 20230253206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => METHODS FOR PREPARING SMALL FEATURES ON A SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/989557 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/989557
Methods for preparing small features on a substrate Nov 16, 2022 Issued
Array ( [id] => 19046728 [patent_doc_number] => 11935848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Package for a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/984908 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8326 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17984908 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/984908
Package for a semiconductor device Nov 9, 2022 Issued
Array ( [id] => 18224737 [patent_doc_number] => 20230063731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => BULK SUBSTRATES WITH A SELF-ALIGNED BURIED POLYCRYSTALLINE LAYER [patent_app_type] => utility [patent_app_number] => 17/983436 [patent_app_country] => US [patent_app_date] => 2022-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17983436 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/983436
Bulk substrates with a self-aligned buried polycrystalline layer Nov 8, 2022 Issued
Array ( [id] => 20230359 [patent_doc_number] => 12419024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => High density static random-access memory [patent_app_type] => utility [patent_app_number] => 18/053451 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5741 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18053451 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/053451
High density static random-access memory Nov 7, 2022 Issued
Array ( [id] => 19964919 [patent_doc_number] => 12334439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Interconnect structure in semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/982045 [patent_app_country] => US [patent_app_date] => 2022-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3402 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982045 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/982045
Interconnect structure in semiconductor devices Nov 6, 2022 Issued
Array ( [id] => 18456391 [patent_doc_number] => 20230197673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/975394 [patent_app_country] => US [patent_app_date] => 2022-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17975394 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/975394
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE Oct 26, 2022 Abandoned
Array ( [id] => 20204155 [patent_doc_number] => 12406939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/954350 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954350 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954350
Semiconductor structure and manufacturing method thereof Sep 27, 2022 Issued
Array ( [id] => 20441478 [patent_doc_number] => 12512320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Semiconductor structure and method for preparing semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/954633 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4653 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954633 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954633
Semiconductor structure and method for preparing semiconductor structure Sep 27, 2022 Issued
Array ( [id] => 19765875 [patent_doc_number] => 12224176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Method for forming fin structure in fin field effect transistor process and fin structure [patent_app_type] => utility [patent_app_number] => 17/950812 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3943 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950812 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/950812
Method for forming fin structure in fin field effect transistor process and fin structure Sep 21, 2022 Issued
Array ( [id] => 20305356 [patent_doc_number] => 12451354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Double patterning method of patterning a substrate [patent_app_type] => utility [patent_app_number] => 17/941331 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 57 [patent_no_of_words] => 5537 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941331 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/941331
Double patterning method of patterning a substrate Sep 8, 2022 Issued
Array ( [id] => 18631788 [patent_doc_number] => 20230290693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => SEMICONDUCTOR MANUFACTURING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/901667 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901667 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901667
SEMICONDUCTOR MANUFACTURING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Aug 31, 2022 Abandoned
Array ( [id] => 18243396 [patent_doc_number] => 20230075707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => METAL STACKS FOR LIGHT EMITTING DIODES FOR BONDING AND/OR OHMIC CONTACT-REFLECTIVE MATERIAL [patent_app_type] => utility [patent_app_number] => 17/901272 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901272 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901272
METAL STACKS FOR LIGHT EMITTING DIODES FOR BONDING AND/OR OHMIC CONTACT-REFLECTIVE MATERIAL Aug 31, 2022 Pending
Array ( [id] => 20332764 [patent_doc_number] => 12463048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Methods for forming semiconductor devices using metal hard masks [patent_app_type] => utility [patent_app_number] => 17/901727 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901727 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901727
Methods for forming semiconductor devices using metal hard masks Aug 31, 2022 Issued
Array ( [id] => 19933344 [patent_doc_number] => 12306547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Method for measuring stitching overlay accuracy of image sensor stitching manufacturing [patent_app_type] => utility [patent_app_number] => 17/893425 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 702 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893425 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893425
Method for measuring stitching overlay accuracy of image sensor stitching manufacturing Aug 22, 2022 Issued
Array ( [id] => 18040237 [patent_doc_number] => 20220384454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => Multi-Layer High-K Gate Dielectric Structure [patent_app_type] => utility [patent_app_number] => 17/884442 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884442 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884442
Multi-layer high-k gate dielectric structure Aug 8, 2022 Issued
Array ( [id] => 17993497 [patent_doc_number] => 20220359534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Active region structure and the forming method thereof [patent_app_type] => utility [patent_app_number] => 17/874309 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874309 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874309
Active region structure and the forming method thereof Jul 26, 2022 Pending
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