Search

Walter H. Swanson

Examiner (ID: 16413, Phone: (571)270-3322 , Office: P/2823 )

Most Active Art Unit
2823
Art Unit(s)
2815, 4137, 2809, 2823
Total Applications
1143
Issued Applications
883
Pending Applications
87
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18093619 [patent_doc_number] => 20220411960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/660713 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17660713 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/660713
Method of manufacturing semiconductor device Apr 25, 2022 Issued
Array ( [id] => 18935533 [patent_doc_number] => 11887977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/728929 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5255 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17728929 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/728929
Semiconductor device and method of fabricating the same Apr 24, 2022 Issued
Array ( [id] => 17765070 [patent_doc_number] => 20220238683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/722623 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722623 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722623
Semiconductor device and manufacturing method thereof Apr 17, 2022 Issued
Array ( [id] => 17764754 [patent_doc_number] => 20220238367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH LOGIC GATES [patent_app_type] => utility [patent_app_number] => 17/718324 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718324 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718324
3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH LOGIC GATES Apr 11, 2022 Abandoned
Array ( [id] => 17765063 [patent_doc_number] => 20220238676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => GATE ALL AROUND DEVICE [patent_app_type] => utility [patent_app_number] => 17/718080 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718080
Gate all around device Apr 10, 2022 Issued
Array ( [id] => 17752701 [patent_doc_number] => 20220230906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH NAND LOGIC [patent_app_type] => utility [patent_app_number] => 17/716274 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716274 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/716274
3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH NAND LOGIC Apr 7, 2022 Abandoned
Array ( [id] => 19199042 [patent_doc_number] => 11996290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Semiconductor structure, method for fabricating thereof, and method for fabricating semiconductor layout [patent_app_type] => utility [patent_app_number] => 17/706613 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5228 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706613 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706613
Semiconductor structure, method for fabricating thereof, and method for fabricating semiconductor layout Mar 28, 2022 Issued
Array ( [id] => 18248944 [patent_doc_number] => 11605540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Method for preparing semiconductor device structure with fine boron nitride spacer patterns [patent_app_type] => utility [patent_app_number] => 17/701965 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12329 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701965
Method for preparing semiconductor device structure with fine boron nitride spacer patterns Mar 22, 2022 Issued
Array ( [id] => 18237809 [patent_doc_number] => 20230070119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/695943 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695943 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695943
Three-dimensional semiconductor structures Mar 15, 2022 Issued
Array ( [id] => 17993231 [patent_doc_number] => 20220359268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => THROUGH WAFER ISOLATION ELEMENT BACKSIDE PROCESSING [patent_app_type] => utility [patent_app_number] => 17/683201 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/683201
THROUGH WAFER ISOLATION ELEMENT BACKSIDE PROCESSING Feb 27, 2022 Pending
Array ( [id] => 17660750 [patent_doc_number] => 20220181215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => GATE FORMATION PROCESS [patent_app_type] => utility [patent_app_number] => 17/682621 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682621
Gate formation process Feb 27, 2022 Issued
Array ( [id] => 18162350 [patent_doc_number] => 20230028943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING STACKED CHIP STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/680877 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680877 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680877
Semiconductor package including stacked chip structure Feb 24, 2022 Issued
Array ( [id] => 17870683 [patent_doc_number] => 20220293420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => METHOD OF FORMING PATTERNS, INTEGRATED CIRCUIT DEVICE, AND METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 17/680996 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680996 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680996
Method of forming patterns, integrated circuit device, and method of manufacturing the integrated circuit device Feb 24, 2022 Issued
Array ( [id] => 17660721 [patent_doc_number] => 20220181186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => 3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/676179 [patent_app_country] => US [patent_app_date] => 2022-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676179 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/676179
3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE Feb 19, 2022 Abandoned
Array ( [id] => 19627025 [patent_doc_number] => 12165874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Semiconductor structure and forming method thereof [patent_app_type] => utility [patent_app_number] => 17/650983 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7254 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650983 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650983
Semiconductor structure and forming method thereof Feb 13, 2022 Issued
Array ( [id] => 18533348 [patent_doc_number] => 20230238424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => METHOD OF MANUFACTURING CAPACITOR ARRAY [patent_app_type] => utility [patent_app_number] => 17/584636 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584636 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584636
Method of manufacturing capacitor array Jan 25, 2022 Issued
Array ( [id] => 17792613 [patent_doc_number] => 20220251704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => PRECURSOR DELIVERY SYSTEM AND METHOD FOR CYCLIC DEPOSITION [patent_app_type] => utility [patent_app_number] => 17/584126 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584126
Precursor delivery system and method for cyclic deposition Jan 24, 2022 Issued
Array ( [id] => 19539530 [patent_doc_number] => 12132087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Method of manufacturing semiconductor structure having air gap [patent_app_type] => utility [patent_app_number] => 17/582726 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 12339 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582726 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582726
Method of manufacturing semiconductor structure having air gap Jan 23, 2022 Issued
Array ( [id] => 17764717 [patent_doc_number] => 20220238330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => HIGH THROUGHPUT DEPOSITION PROCESS [patent_app_type] => utility [patent_app_number] => 17/579487 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579487 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/579487
HIGH THROUGHPUT DEPOSITION PROCESS Jan 18, 2022 Pending
Array ( [id] => 18514583 [patent_doc_number] => 20230230841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/576606 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17576606 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/576606
Semiconductor structure and method for forming the same Jan 13, 2022 Issued
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