
Walter H. Swanson
Examiner (ID: 2415, Phone: (571)270-3322 , Office: P/2823 )
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2823, 2815, 2809, 4137 |
| Total Applications | 1143 |
| Issued Applications | 886 |
| Pending Applications | 77 |
| Abandoned Applications | 216 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18840131
[patent_doc_number] => 11848210
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Semiconductor structure and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 17/567307
[patent_app_country] => US
[patent_app_date] => 2022-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 28
[patent_no_of_words] => 4416
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567307
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/567307 | Semiconductor structure and method of forming the same | Jan 2, 2022 | Issued |
Array
(
[id] => 18131332
[patent_doc_number] => 11557549
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Method of manufacturing semiconductor structure having dummy pattern around array area
[patent_app_type] => utility
[patent_app_number] => 17/563267
[patent_app_country] => US
[patent_app_date] => 2021-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 38
[patent_no_of_words] => 7075
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563267
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/563267 | Method of manufacturing semiconductor structure having dummy pattern around array area | Dec 27, 2021 | Issued |
Array
(
[id] => 17551516
[patent_doc_number] => 20220122858
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/563469
[patent_app_country] => US
[patent_app_date] => 2021-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12626
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563469
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/563469 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE | Dec 27, 2021 | Abandoned |
Array
(
[id] => 18349898
[patent_doc_number] => 20230138009
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-04
[patent_title] => METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/560222
[patent_app_country] => US
[patent_app_date] => 2021-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2953
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560222
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/560222 | Method for forming a semiconductor structure | Dec 21, 2021 | Issued |
Array
(
[id] => 18943587
[patent_doc_number] => 20240038726
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-01
[patent_title] => AI MODULE
[patent_app_type] => utility
[patent_app_number] => 18/264194
[patent_app_country] => US
[patent_app_date] => 2021-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9817
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18264194
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/264194 | AI MODULE | Dec 20, 2021 | Pending |
Array
(
[id] => 18812705
[patent_doc_number] => 20230387042
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => FRONT-END MODULE WITH VERTICALLY STACKED DIE AND CIRCULATOR
[patent_app_type] => utility
[patent_app_number] => 18/266523
[patent_app_country] => US
[patent_app_date] => 2021-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9558
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18266523
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/266523 | FRONT-END MODULE WITH VERTICALLY STACKED DIE AND CIRCULATOR | Dec 12, 2021 | Pending |
Array
(
[id] => 17840952
[patent_doc_number] => 20220278258
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-01
[patent_title] => METHOD FOR INCREASING THE LIGHT OUTPUT OF MICROLED DEVICECS USING QUANTUM DOTS
[patent_app_type] => utility
[patent_app_number] => 17/549543
[patent_app_country] => US
[patent_app_date] => 2021-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6763
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549543
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/549543 | METHOD FOR INCREASING THE LIGHT OUTPUT OF MICROLED DEVICECS USING QUANTUM DOTS | Dec 12, 2021 | Abandoned |
Array
(
[id] => 19229637
[patent_doc_number] => 12009280
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-11
[patent_title] => IC package with heat spreader
[patent_app_type] => utility
[patent_app_number] => 17/547698
[patent_app_country] => US
[patent_app_date] => 2021-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3942
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547698
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/547698 | IC package with heat spreader | Dec 9, 2021 | Issued |
Array
(
[id] => 20229309
[patent_doc_number] => 12417965
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-16
[patent_title] => Interconnect for IC package
[patent_app_type] => utility
[patent_app_number] => 17/536999
[patent_app_country] => US
[patent_app_date] => 2021-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 27
[patent_no_of_words] => 2164
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536999
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/536999 | Interconnect for IC package | Nov 28, 2021 | Issued |
Array
(
[id] => 17630560
[patent_doc_number] => 20220165575
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-26
[patent_title] => METHOD OF FORMING STRUCTURES FOR THRESHOLD VOLTAGE CONTROL
[patent_app_type] => utility
[patent_app_number] => 17/529562
[patent_app_country] => US
[patent_app_date] => 2021-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16494
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529562
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/529562 | METHOD OF FORMING STRUCTURES FOR THRESHOLD VOLTAGE CONTROL | Nov 17, 2021 | Pending |
Array
(
[id] => 18494294
[patent_doc_number] => 11699716
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-11
[patent_title] => Solid-state imaging device
[patent_app_type] => utility
[patent_app_number] => 17/526800
[patent_app_country] => US
[patent_app_date] => 2021-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 61
[patent_no_of_words] => 16758
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526800
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/526800 | Solid-state imaging device | Nov 14, 2021 | Issued |
Array
(
[id] => 17463830
[patent_doc_number] => 20220077136
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE WITH STRENGTHENED PATTERNS
[patent_app_type] => utility
[patent_app_number] => 17/524907
[patent_app_country] => US
[patent_app_date] => 2021-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6664
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524907
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/524907 | Method for fabricating semiconductor structure with strengthened patterns | Nov 11, 2021 | Issued |
Array
(
[id] => 18540847
[patent_doc_number] => 20230245958
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-03
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/007208
[patent_app_country] => US
[patent_app_date] => 2021-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23993
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18007208
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/007208 | SEMICONDUCTOR DEVICE | Nov 10, 2021 | Pending |
Array
(
[id] => 17595881
[patent_doc_number] => 20220145455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-12
[patent_title] => REACTOR AND RELATED METHODS
[patent_app_type] => utility
[patent_app_number] => 17/522224
[patent_app_country] => US
[patent_app_date] => 2021-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10065
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522224
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/522224 | Reactor and related methods | Nov 8, 2021 | Issued |
Array
(
[id] => 18081003
[patent_doc_number] => 20220406615
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-22
[patent_title] => METHOD FOR IMPROVING METAL WORK FUNCTION BOUNDARY EFFECT
[patent_app_type] => utility
[patent_app_number] => 17/522723
[patent_app_country] => US
[patent_app_date] => 2021-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2863
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 304
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522723
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/522723 | Method for improving metal work function boundary effect | Nov 8, 2021 | Issued |
Array
(
[id] => 18796903
[patent_doc_number] => 11830737
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-28
[patent_title] => Semiconductor device and method of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 17/520634
[patent_app_country] => US
[patent_app_date] => 2021-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 46
[patent_no_of_words] => 8659
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520634
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/520634 | Semiconductor device and method of fabricating the same | Nov 5, 2021 | Issued |
Array
(
[id] => 18350867
[patent_doc_number] => 20230138978
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-04
[patent_title] => STRUCTURE AND METHOD TO PATTERN PITCH LINES
[patent_app_type] => utility
[patent_app_number] => 17/453010
[patent_app_country] => US
[patent_app_date] => 2021-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4938
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453010
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/453010 | Structure and method to pattern pitch lines | Oct 31, 2021 | Issued |
Array
(
[id] => 19371661
[patent_doc_number] => 12063766
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-13
[patent_title] => Vertical static random access memory and method of fabricating thereof
[patent_app_type] => utility
[patent_app_number] => 17/514118
[patent_app_country] => US
[patent_app_date] => 2021-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 21241
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17514118
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/514118 | Vertical static random access memory and method of fabricating thereof | Oct 28, 2021 | Issued |
Array
(
[id] => 19277232
[patent_doc_number] => 12027364
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-02
[patent_title] => Method for manufacturing semiconductor device using plasma-enhanced atomic layer deposition
[patent_app_type] => utility
[patent_app_number] => 17/513390
[patent_app_country] => US
[patent_app_date] => 2021-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2906
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 334
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17513390
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/513390 | Method for manufacturing semiconductor device using plasma-enhanced atomic layer deposition | Oct 27, 2021 | Issued |
Array
(
[id] => 19277230
[patent_doc_number] => 12027362
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-02
[patent_title] => Method for manufacturing semiconductor device using plasma-enhanced atomic layer deposition
[patent_app_type] => utility
[patent_app_number] => 17/513055
[patent_app_country] => US
[patent_app_date] => 2021-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3465
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 317
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17513055
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/513055 | Method for manufacturing semiconductor device using plasma-enhanced atomic layer deposition | Oct 27, 2021 | Issued |