Warren H. Kilpatrick

Array ( [id] => 11360233 [patent_doc_number] => 09536890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Semiconductor transistor and flash memory, and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/675754 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7479 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10733225 [patent_doc_number] => 20160079375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 14/639362 [patent_app_country] => US [patent_app_date] => 2015-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14639362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11524668 [patent_doc_number] => 09608080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Method and structure to reduce parasitic capacitance in raised source/drain silicon-on-insulator devices' [patent_app_type] => utility [patent_app_number] => 14/639232 [patent_app_country] => US [patent_app_date] => 2015-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14639232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11510334 [patent_doc_number] => 09601500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Array of non-volatile memory cells with ROM cells' [patent_app_type] => utility [patent_app_number] => 14/639063 [patent_app_country] => US [patent_app_date] => 2015-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2824 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14639063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12174993 [patent_doc_number] => 09893141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Magnetic core, inductor, and method for fabricating the magnetic core' [patent_app_type] => utility [patent_app_number] => 14/632519 [patent_app_country] => US [patent_app_date] => 2015-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14632519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11050772 [patent_doc_number] => 20160247731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'MULTIPLE THRESHOLD VOLTAGE TRIGATE DEVICES USING 3D CONDENSATION' [patent_app_type] => utility [patent_app_number] => 14/629552 [patent_app_country] => US [patent_app_date] => 2015-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14629552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11615670 [patent_doc_number] => 09653533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Multi-layer interconnected spiral capacitor' [patent_app_type] => utility [patent_app_number] => 14/625484 [patent_app_country] => US [patent_app_date] => 2015-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 16404 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14625484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11043709 [patent_doc_number] => 20160240665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'VERTICAL TRANSISTOR AND LOCAL INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/623843 [patent_app_country] => US [patent_app_date] => 2015-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9027 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14623843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12019821 [patent_doc_number] => 09812534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/616985 [patent_app_country] => US [patent_app_date] => 2015-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5018 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14616985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11021258 [patent_doc_number] => 20160218211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'FABRICATION OF A TRANSISTOR INCLUDING A TUNNELING LAYER' [patent_app_type] => utility [patent_app_number] => 14/604544 [patent_app_country] => US [patent_app_date] => 2015-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 12890 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14604544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11321693 [patent_doc_number] => 09520442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-13 [patent_title] => 'Optoelectronic component' [patent_app_type] => utility [patent_app_number] => 14/575913 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3955 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14575913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10208907 [patent_doc_number] => 20150093896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'SEMICONDUCTOR DEVICES HAVING THROUGH-VIAS AND METHODS FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/566828 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 11191 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14566828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10802972 [patent_doc_number] => 20160149128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'Diamond Like Carbon (DLC) as a Thermal Sink in a Selector Stack for Non-Volatile Memory Application' [patent_app_type] => utility [patent_app_number] => 14/553443 [patent_app_country] => US [patent_app_date] => 2014-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14553443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10795222 [patent_doc_number] => 20160141379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'INTEGRATED CIRCUITS WITH MIDDLE OF LINE CAPACITANCE REDUCTION IN SELF-ALIGNED CONTACT PROCESS FLOW AND FABRICATION METHODS' [patent_app_type] => utility [patent_app_number] => 14/541754 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 7126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14541754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11453410 [patent_doc_number] => 09577062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Dual metal gate electrode for reducing threshold voltage' [patent_app_type] => utility [patent_app_number] => 14/524056 [patent_app_country] => US [patent_app_date] => 2014-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6317 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14524056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10733194 [patent_doc_number] => 20160079344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'Electronic Device Including An Isolation Structure' [patent_app_type] => utility [patent_app_number] => 14/524053 [patent_app_country] => US [patent_app_date] => 2014-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6885 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14524053 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13214637 [patent_doc_number] => 10121694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Methods of manufacturing a semiconductor device [patent_app_type] => utility [patent_app_number] => 14/519829 [patent_app_country] => US [patent_app_date] => 2014-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14519829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10765219 [patent_doc_number] => 20160111375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'TEMPORARY BONDING OF PACKAGES TO CARRIER FOR DEPOSITING METAL LAYER FOR SHIELDING' [patent_app_type] => utility [patent_app_number] => 14/517515 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4134 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517515 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11578743 [patent_doc_number] => 09634013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Contact for semiconductor fabrication' [patent_app_type] => utility [patent_app_number] => 14/516278 [patent_app_country] => US [patent_app_date] => 2014-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14516278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10765164 [patent_doc_number] => 20160111320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'T-SHAPED FIN ISOLATION REGION AND METHODS OF FABRICATION' [patent_app_type] => utility [patent_app_number] => 14/515628 [patent_app_country] => US [patent_app_date] => 2014-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14515628 [rel_patent_id] =>[rel_patent_doc_number] =>)