Wasiul Haider

Array ( [id] => 18400249 [patent_doc_number] => 11662382 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-30 [patent_title] => Method and apparatus for contemporary test time reduction for JTAG [patent_app_type] => utility [patent_app_number] => 17/483488 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18072754 [patent_doc_number] => 11531588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Error correction circuit and method for operating the same [patent_app_type] => utility [patent_app_number] => 17/480560 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10826 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17884896 [patent_doc_number] => 20220300373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/470521 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18030700 [patent_doc_number] => 11513889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Parity protection [patent_app_type] => utility [patent_app_number] => 17/458224 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458224 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17762712 [patent_doc_number] => 20220236324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/410744 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18046013 [patent_doc_number] => 11519962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Test circuit [patent_app_type] => utility [patent_app_number] => 17/409871 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5114 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17296107 [patent_doc_number] => 20210391946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => METHOD AND APPARATUS FOR CHANNEL ENCODING AND DECODING IN COMMUNICATION OR BROADCASTING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/409054 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 740 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18209675 [patent_doc_number] => 20230055935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => SELF-CONTAINED BUILT-IN SELF-TEST CIRCUIT WITH PHASE-SHIFTING ABILITIES FOR HIGH-SPEED RECEIVERS [patent_app_type] => utility [patent_app_number] => 17/405173 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17924729 [patent_doc_number] => 11467979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Methods for supporting mismatched transaction granularities [patent_app_type] => utility [patent_app_number] => 17/393006 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 17473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18014418 [patent_doc_number] => 11506710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-22 [patent_title] => Method for testing a circuit system and a circuit system thereof [patent_app_type] => utility [patent_app_number] => 17/388806 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388806 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18586761 [patent_doc_number] => 20230269026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => RATELESS CODING AT LAYER TWO PROTOCOL LAYER [patent_app_type] => utility [patent_app_number] => 18/004648 [patent_app_country] => US [patent_app_date] => 2021-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 78497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18004648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17947160 [patent_doc_number] => 20220334179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => METHOD FOR REAL-TIME FIRMWARE CONFIGURATION AND DEBUGGING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/378924 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17378924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17898447 [patent_doc_number] => 20220308109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SYSTEM AND METHOD OF TESTING SINGLE DUT THROUGH MULTIPLE CORES IN PARALLEL [patent_app_type] => utility [patent_app_number] => 17/375013 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18568383 [patent_doc_number] => 20230258719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => INTEGRATED CIRCUIT MARGIN MEASUREMENT FOR STRUCTURAL TESTING [patent_app_type] => utility [patent_app_number] => 18/014642 [patent_app_country] => US [patent_app_date] => 2021-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18014642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17304004 [patent_doc_number] => 20210399843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => Methods and Devices for Receipt Status Reporting [patent_app_type] => utility [patent_app_number] => 17/365638 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17891709 [patent_doc_number] => 11454671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-27 [patent_title] => Data gating using scan enable pin [patent_app_type] => utility [patent_app_number] => 17/363093 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7714 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17363093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17846036 [patent_doc_number] => 11435400 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-06 [patent_title] => Test coverage rate improvement system for pins of tested circuit board and method thereof [patent_app_type] => utility [patent_app_number] => 17/357429 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2977 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18046015 [patent_doc_number] => 11519964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Phase controlled codec block scan of a partitioned circuit device [patent_app_type] => utility [patent_app_number] => 17/353882 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17278818 [patent_doc_number] => 20210385016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => POLAR CODING SYSTEMS, PROCEDURES, AND SIGNALING [patent_app_type] => utility [patent_app_number] => 17/350054 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17653450 [patent_doc_number] => 11356200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Enhanced polarization weighting to enable scalability in polar code bit distribution [patent_app_type] => utility [patent_app_number] => 17/345380 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 11537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345380 [rel_patent_id] =>[rel_patent_doc_number] =>)