Search

Wasiul Haider

Examiner (ID: 14097, Phone: (571)272-1554 , Office: P/2819 )

Most Active Art Unit
2819
Art Unit(s)
2814, 2812, 2819
Total Applications
776
Issued Applications
673
Pending Applications
75
Abandoned Applications
49

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17752805 [patent_doc_number] => 20220231010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => AN ELECTROSTATIC DISCHARGE (ESD) ARRAY WITH BACK END OF LINE (BEOL) CONNECTION IN A CARRIER WAFER [patent_app_type] => utility [patent_app_number] => 17/150782 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150782 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150782
Electrostatic discharge (ESD) array with back end of line (BEOL) connection in a carrier wafer Jan 14, 2021 Issued
Array ( [id] => 17277990 [patent_doc_number] => 20210384188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => ELECTROSTATIC DISCHARGE DEVICE AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/144354 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144354 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144354
FinFET ESD device with fin-cut isolation region Jan 7, 2021 Issued
Array ( [id] => 16951788 [patent_doc_number] => 20210210480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => TRANSISTOR STRUCTURE FOR ELECTROSTATIC PROTECTION AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/142596 [patent_app_country] => US [patent_app_date] => 2021-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/142596
Transistor structure for electrostatic protection and method for manufacturing same Jan 5, 2021 Issued
Array ( [id] => 18464481 [patent_doc_number] => 11688778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Semiconductor device including three-dimensional field-effect transistor with curved multi-layered source/drain pattern [patent_app_type] => utility [patent_app_number] => 17/141513 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 9767 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141513 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141513
Semiconductor device including three-dimensional field-effect transistor with curved multi-layered source/drain pattern Jan 4, 2021 Issued
Array ( [id] => 18983612 [patent_doc_number] => 11908801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Connecting component, display panel, and display device [patent_app_type] => utility [patent_app_number] => 17/276160 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5523 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17276160 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/276160
Connecting component, display panel, and display device Dec 29, 2020 Issued
Array ( [id] => 17070900 [patent_doc_number] => 20210273117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/137643 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137643 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137643
Semiconductor device with a lifetime killer region in the substrate Dec 29, 2020 Issued
Array ( [id] => 18081328 [patent_doc_number] => 20220406940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/261015 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17261015 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/261015
Thin film transistor and manufacturing method thereof Dec 28, 2020 Issued
Array ( [id] => 19627174 [patent_doc_number] => 12166023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Light-emitting substrate and preparation method thereof, light-emitting module, and display module [patent_app_type] => utility [patent_app_number] => 17/603011 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 8232 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17603011 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/603011
Light-emitting substrate and preparation method thereof, light-emitting module, and display module Dec 27, 2020 Issued
Array ( [id] => 18533362 [patent_doc_number] => 20230238438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/002642 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18002642 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/002642
Semiconductor device and method for manufacturing the same Dec 21, 2020 Issued
Array ( [id] => 18331951 [patent_doc_number] => 11637209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => JFET with implant isolation [patent_app_type] => utility [patent_app_number] => 17/131568 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 38 [patent_no_of_words] => 10194 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131568 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131568
JFET with implant isolation Dec 21, 2020 Issued
Array ( [id] => 16812112 [patent_doc_number] => 20210134667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 17/120696 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120696 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120696
Contact plug with impurity variation Dec 13, 2020 Issued
Array ( [id] => 16873851 [patent_doc_number] => 20210167318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => OPTOELECTRONIC ASSEMBLY AND METHOD FOR PRODUCING AN OPTOELECTRONIC ASSEMBLY [patent_app_type] => utility [patent_app_number] => 17/120524 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120524
Optoelectronic assembly and method for producing an optoelectronic assembly Dec 13, 2020 Issued
Array ( [id] => 16920554 [patent_doc_number] => 20210193646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => Short Circuit Protection Structure in MOS-Gated Power Devices [patent_app_type] => utility [patent_app_number] => 17/120932 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120932 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120932
Short circuit protection structure in MOS-gated power devices Dec 13, 2020 Issued
Array ( [id] => 18054212 [patent_doc_number] => 11527607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Integrated circuits using guard rings for ESD systems [patent_app_type] => utility [patent_app_number] => 17/120902 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4997 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120902 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120902
Integrated circuits using guard rings for ESD systems Dec 13, 2020 Issued
Array ( [id] => 16873721 [patent_doc_number] => 20210167188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => PROCESS OF FORMING HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND HEMT FORMED BY THE SAME [patent_app_type] => utility [patent_app_number] => 17/118502 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118502 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/118502
PROCESS OF FORMING HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND HEMT FORMED BY THE SAME Dec 9, 2020 Abandoned
Array ( [id] => 17649976 [patent_doc_number] => 11352690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Metal oxide film, semiconductor device, and display device [patent_app_type] => utility [patent_app_number] => 17/113653 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 212 [patent_no_of_words] => 61743 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113653 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113653
Metal oxide film, semiconductor device, and display device Dec 6, 2020 Issued
Array ( [id] => 17661009 [patent_doc_number] => 20220181474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => SILICON CONTROLLED RECTIFIER WITH A GATE ELECTRODE FOR ELECTROSTATIC DISCHARGE PROTECTION [patent_app_type] => utility [patent_app_number] => 17/114391 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114391 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114391
Silicon controlled rectifier with a gate electrode for electrostatic discharge protection Dec 6, 2020 Issued
Array ( [id] => 17645491 [patent_doc_number] => 20220173230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => BIPOLAR JUNCTION TRANSISTOR (BJT) STRUCTURE AND RELATED METHOD [patent_app_type] => utility [patent_app_number] => 17/109464 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109464 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109464
Bipolar junction transistor (BJT) structure and related method Dec 1, 2020 Issued
Array ( [id] => 17239553 [patent_doc_number] => 11183444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Packaging of a semiconductor device with a plurality of leads [patent_app_type] => utility [patent_app_number] => 17/109675 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 6423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109675 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109675
Packaging of a semiconductor device with a plurality of leads Dec 1, 2020 Issued
Array ( [id] => 17486234 [patent_doc_number] => 20220093738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => FDSOI DEVICE STRUCTURE AND PREPARATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/100544 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100544 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/100544
FDSOI device structure and preparation method thereof Nov 19, 2020 Issued
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