Search

Wasiul Haider

Examiner (ID: 637, Phone: (571)272-1554 , Office: P/2819 )

Most Active Art Unit
2819
Art Unit(s)
2814, 2812, 2819
Total Applications
743
Issued Applications
651
Pending Applications
67
Abandoned Applications
49

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16944227 [patent_doc_number] => 11056478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Metal gate structure cutting process [patent_app_type] => utility [patent_app_number] => 16/203755 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 58 [patent_no_of_words] => 9540 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203755 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203755
Metal gate structure cutting process Nov 28, 2018 Issued
Array ( [id] => 16560609 [patent_doc_number] => 20210005758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => TUNNELING FIELD EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/767479 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16767479 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/767479
Tunneling field effect transistor Nov 27, 2018 Issued
Array ( [id] => 17716583 [patent_doc_number] => 11380581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Interconnect structures of semiconductor devices having a via structure through an upper conductive line [patent_app_type] => utility [patent_app_number] => 16/185015 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 4428 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16185015 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/185015
Interconnect structures of semiconductor devices having a via structure through an upper conductive line Nov 8, 2018 Issued
Array ( [id] => 14079177 [patent_doc_number] => 20190088476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => BUFFER LAYERS HAVING COMPOSITE STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/179419 [patent_app_country] => US [patent_app_date] => 2018-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16179419 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/179419
Buffer layers having composite structures Nov 1, 2018 Issued
Array ( [id] => 13936461 [patent_doc_number] => 20190051746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/162347 [patent_app_country] => US [patent_app_date] => 2018-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12775 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16162347 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/162347
Semiconductor device and manufacturing method thereof Oct 15, 2018 Issued
Array ( [id] => 18054287 [patent_doc_number] => 11527683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Laser printing of color converter devices on micro LED display devices and methods [patent_app_type] => utility [patent_app_number] => 16/157179 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 6912 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157179 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/157179
Laser printing of color converter devices on micro LED display devices and methods Oct 10, 2018 Issued
Array ( [id] => 15717999 [patent_doc_number] => 20200105767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => Conductive Feature Formation [patent_app_type] => utility [patent_app_number] => 16/145432 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145432 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145432
Conductive feature formation Sep 27, 2018 Issued
Array ( [id] => 15889677 [patent_doc_number] => 10651194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Semiconductor device including dielectric layer [patent_app_type] => utility [patent_app_number] => 16/142637 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 12473 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16142637 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/142637
Semiconductor device including dielectric layer Sep 25, 2018 Issued
Array ( [id] => 15641321 [patent_doc_number] => 10593665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Field effect transistor (FET) structure with integrated gate connected diodes [patent_app_type] => utility [patent_app_number] => 16/135606 [patent_app_country] => US [patent_app_date] => 2018-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4307 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16135606 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/135606
Field effect transistor (FET) structure with integrated gate connected diodes Sep 18, 2018 Issued
Array ( [id] => 16601747 [patent_doc_number] => 20210028278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => IGBT CHIP HAVING COMPOSITE GATE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/969604 [patent_app_country] => US [patent_app_date] => 2018-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4119 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16969604 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/969604
IGBT chip having mixed gate structure Sep 17, 2018 Issued
Array ( [id] => 14078561 [patent_doc_number] => 20190088168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => DISPLAY DEVICE USING SEMICONDUCTOR LIGHT-EMITTING DIODE [patent_app_type] => utility [patent_app_number] => 16/129983 [patent_app_country] => US [patent_app_date] => 2018-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11365 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16129983 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/129983
Display device using semiconductor light-emitting diode Sep 12, 2018 Issued
Array ( [id] => 14049865 [patent_doc_number] => 20190081040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/127904 [patent_app_country] => US [patent_app_date] => 2018-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16127904 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/127904
Zener diode with semiconductor region annularly surrounding anode Sep 10, 2018 Issued
Array ( [id] => 14050093 [patent_doc_number] => 20190081154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => PROCESS OF FORMING HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND HEMT FORMED BY THE SAME [patent_app_type] => utility [patent_app_number] => 16/127896 [patent_app_country] => US [patent_app_date] => 2018-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16127896 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/127896
Process of forming high electron mobility transistor (HEMT) and HEMT formed by the same Sep 10, 2018 Issued
Array ( [id] => 13832923 [patent_doc_number] => 20190019946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => METHODS FOR ADDITIVE FORMATION OF A STT MRAM STACK [patent_app_type] => utility [patent_app_number] => 16/127042 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16127042 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/127042
Methods for additive formation of a STT MRAM stack Sep 9, 2018 Issued
Array ( [id] => 13740733 [patent_doc_number] => 20180374836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => Semiconductor Packages and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 16/118656 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16118656 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/118656
Packaged die and RDL with bonding structures therebetween Aug 30, 2018 Issued
Array ( [id] => 15857909 [patent_doc_number] => 10644257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 16/113478 [patent_app_country] => US [patent_app_date] => 2018-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4994 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16113478 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/113478
Display device Aug 26, 2018 Issued
Array ( [id] => 13740951 [patent_doc_number] => 20180374945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/113443 [patent_app_country] => US [patent_app_date] => 2018-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16113443 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/113443
Semiconductor structure and manufacturing method thereof Aug 26, 2018 Issued
Array ( [id] => 15971345 [patent_doc_number] => 20200169424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => PHYSICALLY UNCLONABLE FUNCTION DEVICE, METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 16/636690 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16636690 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/636690
Physically unclonable function device, method and apparatus Aug 6, 2018 Issued
Array ( [id] => 13571427 [patent_doc_number] => 20180337261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => FORMING STACKED NANOWIRE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/047042 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16047042 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/047042
Forming stacked nanowire semiconductor device Jul 26, 2018 Issued
Array ( [id] => 16194391 [patent_doc_number] => 20200235240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => Diamond MIS Transistor [patent_app_type] => utility [patent_app_number] => 16/630905 [patent_app_country] => US [patent_app_date] => 2018-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16630905 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/630905
Diamond MIS transistor Jul 17, 2018 Issued
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