
Wasiul Haider
Examiner (ID: 637, Phone: (571)272-1554 , Office: P/2819 )
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2814, 2812, 2819 |
| Total Applications | 743 |
| Issued Applications | 651 |
| Pending Applications | 67 |
| Abandoned Applications | 49 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16700004
[patent_doc_number] => 10950612
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-16
[patent_title] => Three dimensional semiconductor memory with residual memory layer
[patent_app_type] => utility
[patent_app_number] => 15/981928
[patent_app_country] => US
[patent_app_date] => 2018-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 38
[patent_no_of_words] => 6717
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981928
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/981928 | Three dimensional semiconductor memory with residual memory layer | May 16, 2018 | Issued |
Array
(
[id] => 15154409
[patent_doc_number] => 20190355682
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-21
[patent_title] => Integrated Circuit Structures And Methods Of Forming An Opening In A Material
[patent_app_type] => utility
[patent_app_number] => 15/981599
[patent_app_country] => US
[patent_app_date] => 2018-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5120
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981599
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/981599 | Integrated circuit structures and methods of forming an opening in a material | May 15, 2018 | Issued |
Array
(
[id] => 16668647
[patent_doc_number] => 10937906
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-02
[patent_title] => Semiconductor device including fin structures and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 15/974227
[patent_app_country] => US
[patent_app_date] => 2018-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 6546
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15974227
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/974227 | Semiconductor device including fin structures and manufacturing method thereof | May 7, 2018 | Issued |
Array
(
[id] => 16433066
[patent_doc_number] => 10833165
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-10
[patent_title] => Asymmetric air spacer gate-controlled device with reduced parasitic capacitance
[patent_app_type] => utility
[patent_app_number] => 15/967540
[patent_app_country] => US
[patent_app_date] => 2018-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5420
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967540
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/967540 | Asymmetric air spacer gate-controlled device with reduced parasitic capacitance | Apr 29, 2018 | Issued |
Array
(
[id] => 15045607
[patent_doc_number] => 20190333808
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-31
[patent_title] => Semiconductor Device and Method
[patent_app_type] => utility
[patent_app_number] => 15/967497
[patent_app_country] => US
[patent_app_date] => 2018-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9542
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967497
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/967497 | Semiconductor device and method | Apr 29, 2018 | Issued |
Array
(
[id] => 15030481
[patent_doc_number] => 20190326245
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-24
[patent_title] => FLIP CHIP INTEGRATED CIRCUIT PACKAGES WITH SPACERS
[patent_app_type] => utility
[patent_app_number] => 15/956534
[patent_app_country] => US
[patent_app_date] => 2018-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6544
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15956534
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/956534 | Flip chip integrated circuit packages with spacers | Apr 17, 2018 | Issued |
Array
(
[id] => 15000023
[patent_doc_number] => 20190318969
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-17
[patent_title] => MASKLESS EPITAXIAL GROWTH OF PHOSPHORUS-DOPED Si AND BORON-DOPED SiGe (Ge) FOR ADVANCED SOURCE/DRAIN CONTACT
[patent_app_type] => utility
[patent_app_number] => 15/954133
[patent_app_country] => US
[patent_app_date] => 2018-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6479
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15954133
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/954133 | Maskless epitaxial growth of phosphorus-doped Si and boron-doped SiGe (Ge) for advanced source/drain contact | Apr 15, 2018 | Issued |
Array
(
[id] => 13485335
[patent_doc_number] => 20180294210
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-10-11
[patent_title] => PACKAGE WITH COMPONENT CONNECTED WITH CARRIER VIA SPACER PARTICLES
[patent_app_type] => utility
[patent_app_number] => 15/949533
[patent_app_country] => US
[patent_app_date] => 2018-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7130
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949533
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/949533 | Package with component connected with carrier via spacer particles | Apr 9, 2018 | Issued |
Array
(
[id] => 15300481
[patent_doc_number] => 20190393376
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-26
[patent_title] => Method for Producing a Component and Component for an Electronic Device
[patent_app_type] => utility
[patent_app_number] => 16/485414
[patent_app_country] => US
[patent_app_date] => 2018-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6843
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16485414
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/485414 | Method of separating a component using predetermined breaking position and a component obatined by such method | Mar 19, 2018 | Issued |
Array
(
[id] => 14707141
[patent_doc_number] => 10381330
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-13
[patent_title] => Sacrificial alignment ring and self-soldering vias for wafer bonding
[patent_app_type] => utility
[patent_app_number] => 15/921563
[patent_app_country] => US
[patent_app_date] => 2018-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 2596
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15921563
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/921563 | Sacrificial alignment ring and self-soldering vias for wafer bonding | Mar 13, 2018 | Issued |
Array
(
[id] => 13528433
[patent_doc_number] => 20180315759
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-01
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/920468
[patent_app_country] => US
[patent_app_date] => 2018-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1978
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15920468
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/920468 | Semiconductor device and method for fabricating the same | Mar 13, 2018 | Issued |
Array
(
[id] => 16293577
[patent_doc_number] => 10770432
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-08
[patent_title] => ASICS face to face self assembly
[patent_app_type] => utility
[patent_app_number] => 15/919871
[patent_app_country] => US
[patent_app_date] => 2018-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 5369
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 333
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919871
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/919871 | ASICS face to face self assembly | Mar 12, 2018 | Issued |
Array
(
[id] => 13461211
[patent_doc_number] => 20180282148
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-10-04
[patent_title] => PRESSURE SENSOR, MANUFACTURING METHOD OF PRESSURE SENSOR, PRESSURE SENSOR MODULE, ELECTRONIC DEVICE, AND VEHICLE
[patent_app_type] => utility
[patent_app_number] => 15/919764
[patent_app_country] => US
[patent_app_date] => 2018-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15184
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919764
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/919764 | PRESSURE SENSOR, MANUFACTURING METHOD OF PRESSURE SENSOR, PRESSURE SENSOR MODULE, ELECTRONIC DEVICE, AND VEHICLE | Mar 12, 2018 | Abandoned |
Array
(
[id] => 16379467
[patent_doc_number] => 20200328310
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-15
[patent_title] => THIN FILM TRANSISTOR AND ARRAY SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 16/304126
[patent_app_country] => US
[patent_app_date] => 2018-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6990
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16304126
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/304126 | THIN FILM TRANSISTOR AND ARRAY SUBSTRATE | Mar 10, 2018 | Abandoned |
Array
(
[id] => 13405791
[patent_doc_number] => 20180254438
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-06
[patent_title] => Top Emitting OLEDs with Increased Brightness
[patent_app_type] => utility
[patent_app_number] => 15/909434
[patent_app_country] => US
[patent_app_date] => 2018-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1872
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909434
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/909434 | Top Emitting OLEDs with Increased Brightness | Feb 28, 2018 | Abandoned |
Array
(
[id] => 17048222
[patent_doc_number] => 11101413
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-24
[patent_title] => Semiconductor nanoparticles, method of producing the semiconductor nanoparticles, and light-emitting device
[patent_app_type] => utility
[patent_app_number] => 16/489214
[patent_app_country] => US
[patent_app_date] => 2018-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 11673
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 31
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16489214
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/489214 | Semiconductor nanoparticles, method of producing the semiconductor nanoparticles, and light-emitting device | Feb 27, 2018 | Issued |
Array
(
[id] => 16819923
[patent_doc_number] => 11004761
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-11
[patent_title] => Packaging of a semiconductor device with dual sealing materials
[patent_app_type] => utility
[patent_app_number] => 16/485183
[patent_app_country] => US
[patent_app_date] => 2018-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 21
[patent_no_of_words] => 12228
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 303
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16485183
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/485183 | Packaging of a semiconductor device with dual sealing materials | Feb 27, 2018 | Issued |
Array
(
[id] => 12872809
[patent_doc_number] => 20180182778
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-28
[patent_title] => STRUCTURE AND METHOD FOR FULLY DEPLETED SILICON ON INSULATOR STRUCTURE FOR THRESHOLD VOLTAGE MODIFICATION
[patent_app_type] => utility
[patent_app_number] => 15/901997
[patent_app_country] => US
[patent_app_date] => 2018-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5475
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15901997
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/901997 | Structure and method for fully depleted silicon on insulator structure for threshold voltage modification | Feb 21, 2018 | Issued |
Array
(
[id] => 12823885
[patent_doc_number] => 20180166467
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-14
[patent_title] => ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/893699
[patent_app_country] => US
[patent_app_date] => 2018-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8742
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15893699
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/893699 | Array substrate, display panel and display device | Feb 11, 2018 | Issued |
Array
(
[id] => 13755133
[patent_doc_number] => 10170520
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-01-01
[patent_title] => Negative-capacitance steep-switch field effect transistor with integrated bi-stable resistive system
[patent_app_type] => utility
[patent_app_number] => 15/894128
[patent_app_country] => US
[patent_app_date] => 2018-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 7055
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15894128
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/894128 | Negative-capacitance steep-switch field effect transistor with integrated bi-stable resistive system | Feb 11, 2018 | Issued |