Search

Wasiul Haider

Examiner (ID: 17919, Phone: (571)272-1554 , Office: P/2819 )

Most Active Art Unit
2819
Art Unit(s)
2819, 2814, 2812
Total Applications
769
Issued Applications
672
Pending Applications
69
Abandoned Applications
49

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19315064 [patent_doc_number] => 12040895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-16 [patent_title] => Management of message transmission using forward error correction [patent_app_type] => utility [patent_app_number] => 18/069575 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9082 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18069575 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/069575
Management of message transmission using forward error correction Dec 20, 2022 Issued
Array ( [id] => 19583130 [patent_doc_number] => 12149263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Computationally efficient and bitrate scalable soft vector quantization [patent_app_type] => utility [patent_app_number] => 18/079441 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9863 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18079441 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/079441
Computationally efficient and bitrate scalable soft vector quantization Dec 11, 2022 Issued
Array ( [id] => 18438845 [patent_doc_number] => 20230186140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => METHOD OF PROCEDURAL THRESHOLDS IN QAP-BASED FAULT TOLERANCE QUANTUM COMPUTATION [patent_app_type] => utility [patent_app_number] => 18/077244 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077244
Method of procedural thresholds in QAP-based fault tolerance quantum computation Dec 7, 2022 Issued
Array ( [id] => 18710535 [patent_doc_number] => 20230333160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => FAN-OUT BUFFER WITH SKEW CONTROL FUNCTION, OPERATING METHOD THEREOF, AND PROBE CARD INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/075542 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18075542 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/075542
Fan-out buffer with skew control function, operating method thereof, and probe card including the same Dec 5, 2022 Issued
Array ( [id] => 18269477 [patent_doc_number] => 20230090719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => PAYLOAD DISTRIBUTION IN SOLID STATE DRIVES [patent_app_type] => utility [patent_app_number] => 17/993121 [patent_app_country] => US [patent_app_date] => 2022-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17993121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/993121
Payload distribution in solid state drives Nov 22, 2022 Issued
Array ( [id] => 19230193 [patent_doc_number] => 12009838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-11 [patent_title] => Physical layout of the Floquet code based on square-octagon lattice [patent_app_type] => utility [patent_app_number] => 17/990299 [patent_app_country] => US [patent_app_date] => 2022-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 71 [patent_figures_cnt] => 90 [patent_no_of_words] => 17511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17990299 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/990299
Physical layout of the Floquet code based on square-octagon lattice Nov 17, 2022 Issued
Array ( [id] => 19679064 [patent_doc_number] => 12190935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Memory and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/980141 [patent_app_country] => US [patent_app_date] => 2022-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4383 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17980141 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/980141
Memory and operation method thereof Nov 2, 2022 Issued
Array ( [id] => 18548884 [patent_doc_number] => 11722247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Method and apparatus for channel encoding and decoding in communication or broadcasting system [patent_app_type] => utility [patent_app_number] => 17/979289 [patent_app_country] => US [patent_app_date] => 2022-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 62 [patent_no_of_words] => 21312 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 2155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17979289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/979289
Method and apparatus for channel encoding and decoding in communication or broadcasting system Nov 1, 2022 Issued
Array ( [id] => 19028682 [patent_doc_number] => 11928039 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-12 [patent_title] => Data-transfer test mode [patent_app_type] => utility [patent_app_number] => 18/051603 [patent_app_country] => US [patent_app_date] => 2022-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 18525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051603 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051603
Data-transfer test mode Oct 31, 2022 Issued
Array ( [id] => 18310417 [patent_doc_number] => 20230114317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => Storage System Parity Based On System Characteristics [patent_app_type] => utility [patent_app_number] => 18/051547 [patent_app_country] => US [patent_app_date] => 2022-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051547 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051547
Storage system parity based on system characteristics Oct 31, 2022 Issued
Array ( [id] => 19028666 [patent_doc_number] => 11928023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-12 [patent_title] => Techniques for indicating a write link error [patent_app_type] => utility [patent_app_number] => 18/050679 [patent_app_country] => US [patent_app_date] => 2022-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 12342 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18050679 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/050679
Techniques for indicating a write link error Oct 27, 2022 Issued
Array ( [id] => 19168991 [patent_doc_number] => 11984910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-14 [patent_title] => Reinforcement learning-enabled low-density parity check decoder [patent_app_type] => utility [patent_app_number] => 18/050387 [patent_app_country] => US [patent_app_date] => 2022-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 15520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18050387 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/050387
Reinforcement learning-enabled low-density parity check decoder Oct 26, 2022 Issued
Array ( [id] => 18297475 [patent_doc_number] => 20230107161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => Parity Checking Method for Qubit and Superconducting Quantum Chip [patent_app_type] => utility [patent_app_number] => 18/050281 [patent_app_country] => US [patent_app_date] => 2022-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18050281 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/050281
Parity checking method for qubit and superconducting quantum chip Oct 26, 2022 Issued
Array ( [id] => 18141561 [patent_doc_number] => 20230015404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/949287 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949287 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/949287
Memory system and data processing system including the same Sep 20, 2022 Issued
Array ( [id] => 19052323 [patent_doc_number] => 20240094292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => System of Performing Boundary Scan Test on Pin Through Test Point and Method Thereof [patent_app_type] => utility [patent_app_number] => 17/948703 [patent_app_country] => US [patent_app_date] => 2022-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5993 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17948703 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/948703
System of performing boundary scan test on pin through test point and method thereof Sep 19, 2022 Issued
Array ( [id] => 19355152 [patent_doc_number] => 12055587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Integrated test circuit, test assembly and method for testing an integrated circuit [patent_app_type] => utility [patent_app_number] => 17/947495 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5506 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17947495 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/947495
Integrated test circuit, test assembly and method for testing an integrated circuit Sep 18, 2022 Issued
Array ( [id] => 19052322 [patent_doc_number] => 20240094291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => FLEXIBLE ONE-HOT DECODING LOGIC FOR CLOCK CONTROLS [patent_app_type] => utility [patent_app_number] => 17/932808 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932808 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932808
Flexible one-hot decoding logic for clock controls Sep 15, 2022 Issued
Array ( [id] => 18949215 [patent_doc_number] => 11892505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-06 [patent_title] => Debug and trace circuit in lockstep architectures, associated method, processing system, and apparatus [patent_app_type] => utility [patent_app_number] => 17/945576 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7440 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945576 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/945576
Debug and trace circuit in lockstep architectures, associated method, processing system, and apparatus Sep 14, 2022 Issued
Array ( [id] => 18911348 [patent_doc_number] => 11874325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Integrated circuit, test assembly and method for testing an integrated circuit [patent_app_type] => utility [patent_app_number] => 17/944239 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17944239 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/944239
Integrated circuit, test assembly and method for testing an integrated circuit Sep 13, 2022 Issued
Array ( [id] => 18592071 [patent_doc_number] => 11740969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Detecting and recovering a corrupted non-volatile random-access memory [patent_app_type] => utility [patent_app_number] => 17/900247 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17900247 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/900247
Detecting and recovering a corrupted non-volatile random-access memory Aug 30, 2022 Issued
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