Search

Wei Chan

Examiner (ID: 12485, Phone: (571)272-5177 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2844, 2845
Total Applications
794
Issued Applications
593
Pending Applications
72
Abandoned Applications
151

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19852815 [patent_doc_number] => 20250098166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE WITH A THREE-DIMENSIONAL STACKED MEMORY CELL STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/964178 [patent_app_country] => US [patent_app_date] => 2024-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18964178 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/964178
SEMICONDUCTOR MEMORY DEVICE WITH A THREE-DIMENSIONAL STACKED MEMORY CELL STRUCTURE Nov 28, 2024 Pending
Array ( [id] => 19986760 [patent_doc_number] => 20250124982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => APPARATUS AND METHODS INCLUDING SOURCE GATES [patent_app_type] => utility [patent_app_number] => 18/932143 [patent_app_country] => US [patent_app_date] => 2024-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932143 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/932143
APPARATUS AND METHODS INCLUDING SOURCE GATES Oct 29, 2024 Pending
Array ( [id] => 19749199 [patent_doc_number] => 20250037764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => ReRAM MEMORY ARRAY THAT INCLUDES ReRAM MEMORY CELLS HAVING A ReRAM DEVICE AND TWO SERIES-CONNECTED SELECT TRANSISTORS THAT CAN BE SELECTED FOR PROGRAMMING [patent_app_type] => utility [patent_app_number] => 18/913162 [patent_app_country] => US [patent_app_date] => 2024-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18913162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/913162
ReRAM MEMORY ARRAY THAT INCLUDES ReRAM MEMORY CELLS HAVING A ReRAM DEVICE AND TWO SERIES-CONNECTED SELECT TRANSISTORS THAT CAN BE SELECTED FOR PROGRAMMING Oct 10, 2024 Pending
Array ( [id] => 20422837 [patent_doc_number] => 20250384922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => EVALUATION CIRCUIT FOR STATIC RANDOM-ACCESS MEMORY OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/889380 [patent_app_country] => US [patent_app_date] => 2024-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18889380 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/889380
EVALUATION CIRCUIT FOR STATIC RANDOM-ACCESS MEMORY OPERATIONS Sep 18, 2024 Pending
Array ( [id] => 19712359 [patent_doc_number] => 20250022501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => BALANCED NEGATIVE BITLINE VOLTAGE FOR A WRITE ASSIST CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/773284 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773284 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773284
BALANCED NEGATIVE BITLINE VOLTAGE FOR A WRITE ASSIST CIRCUIT Jul 14, 2024 Pending
Array ( [id] => 19531496 [patent_doc_number] => 20240355398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => BIAS CONTROL FOR MEMORY CELLS WITH MULTIPLE GATE ELECTRODES [patent_app_type] => utility [patent_app_number] => 18/758483 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758483 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758483
BIAS CONTROL FOR MEMORY CELLS WITH MULTIPLE GATE ELECTRODES Jun 27, 2024 Pending
Array ( [id] => 19893041 [patent_doc_number] => 20250118353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/746473 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746473 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746473
APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES Jun 17, 2024 Pending
Array ( [id] => 19500121 [patent_doc_number] => 20240339139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY STRING AND PLURALITY OF SELECT TRANSITSTORS AND METHOD INCLUDING A WRITE OPERATION [patent_app_type] => utility [patent_app_number] => 18/746238 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 466 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746238
Semiconductor memory device including memory string and plurality of select transitstors and method including a write operation Jun 17, 2024 Issued
Array ( [id] => 19893040 [patent_doc_number] => 20250118352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/746447 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746447 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746447
APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES Jun 17, 2024 Pending
Array ( [id] => 19986742 [patent_doc_number] => 20250124964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => APPARATUSES AND METHODS FOR PER ROW ACTIVATION COUNTER TESTING [patent_app_type] => utility [patent_app_number] => 18/745068 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745068 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/745068
APPARATUSES AND METHODS FOR PER ROW ACTIVATION COUNTER TESTING Jun 16, 2024 Pending
Array ( [id] => 19435736 [patent_doc_number] => 20240304234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => MEMORY DEVICE AND METHOD OF CONTROLLING ROW HAMMER [patent_app_type] => utility [patent_app_number] => 18/669714 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669714 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/669714
MEMORY DEVICE AND METHOD OF CONTROLLING ROW HAMMER May 20, 2024 Pending
Array ( [id] => 19406868 [patent_doc_number] => 20240290379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => MANAGING MEMORY BASED ON ACCESS DURATION [patent_app_type] => utility [patent_app_number] => 18/656156 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656156 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/656156
MANAGING MEMORY BASED ON ACCESS DURATION May 5, 2024 Pending
Array ( [id] => 19559623 [patent_doc_number] => 20240371415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => METHODS FOR EFFICIENT 3D SRAM-BASED COMPUTE-IN-MEMORY [patent_app_type] => utility [patent_app_number] => 18/653788 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653788 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653788
Methods for efficient 3D SRAM-based compute-in-memory May 1, 2024 Issued
Array ( [id] => 19384850 [patent_doc_number] => 20240274720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => CONCURRENT COMPENSATION IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/642326 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642326 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/642326
CONCURRENT COMPENSATION IN A MEMORY SYSTEM Apr 21, 2024 Pending
Array ( [id] => 20313523 [patent_doc_number] => 20250331152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => COMPACT GAIN CELL [patent_app_type] => utility [patent_app_number] => 18/637652 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637652 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637652
COMPACT GAIN CELL Apr 16, 2024 Pending
Array ( [id] => 19363933 [patent_doc_number] => 20240265967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => NON-VOLATILE CONTENT ADDRESSABLE MEMORY DEVICE HAVING SIMPLE CELL CONFIGURATION AND OPERATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/621853 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621853 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/621853
NON-VOLATILE CONTENT ADDRESSABLE MEMORY DEVICE HAVING SIMPLE CELL CONFIGURATION AND OPERATING METHOD OF THE SAME Mar 28, 2024 Pending
Array ( [id] => 20495176 [patent_doc_number] => 12537052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Memories, operation methods thereof and memory systems [patent_app_type] => utility [patent_app_number] => 18/614153 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6218 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614153 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614153
Memories, operation methods thereof and memory systems Mar 21, 2024 Issued
Array ( [id] => 20222747 [patent_doc_number] => 20250285678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => DYNAMIC ANALOG CONTENT ADDRESSABLE MEMORY [patent_app_type] => utility [patent_app_number] => 18/598873 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/598873
DYNAMIC ANALOG CONTENT ADDRESSABLE MEMORY Mar 6, 2024 Pending
Array ( [id] => 20002077 [patent_doc_number] => 20250140299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING SAMPLING CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/581376 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581376 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581376
SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING SAMPLING CIRCUIT Feb 19, 2024 Pending
Array ( [id] => 19350043 [patent_doc_number] => 20240259007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => RECEIVER INCLUDING A PULSE AMPLITUDE MODULATION DECODER, AND A MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/428045 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5888 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428045 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428045
Receiver including a pulse amplitude modulation decoder, and a memory device including the same Jan 30, 2024 Issued
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