Search

Wei Po Eric Kao

Examiner (ID: 17393, Phone: (571)270-3128 , Office: P/2464 )

Most Active Art Unit
2464
Art Unit(s)
2616, 2416, 2464
Total Applications
347
Issued Applications
269
Pending Applications
4
Abandoned Applications
78

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18821206 [patent_doc_number] => 20230395547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/205329 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205329 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/205329
Semiconductor device and method of manufacturing the same Jun 1, 2023 Issued
Array ( [id] => 20598276 [patent_doc_number] => 12582017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Bonding layer and process [patent_app_type] => utility [patent_app_number] => 18/320791 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 2120 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320791 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320791
Bonding layer and process May 18, 2023 Issued
Array ( [id] => 18633629 [patent_doc_number] => 20230292556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/198163 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18198163 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/198163
Display apparatus that includes concavo-convex structure on upper surface of pixel defining layer and method of manufacturing the same May 15, 2023 Issued
Array ( [id] => 20332903 [patent_doc_number] => 12463188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Flip-chip packaged power transistor module having built-in gate driver [patent_app_type] => utility [patent_app_number] => 18/197607 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197607 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/197607
Flip-chip packaged power transistor module having built-in gate driver May 14, 2023 Issued
Array ( [id] => 19575446 [patent_doc_number] => 20240379738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => STRUCTURE AND FORMATION METHOD OF INTEGRATED CHIPS PACKAGE WITH CAPACITOR [patent_app_type] => utility [patent_app_number] => 18/314939 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314939 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314939
STRUCTURE AND FORMATION METHOD OF INTEGRATED CHIPS PACKAGE WITH CAPACITOR May 9, 2023 Pending
Array ( [id] => 18600269 [patent_doc_number] => 20230275070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/195096 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18195096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/195096
Chip package structure and manufacturing method thereof May 8, 2023 Issued
Array ( [id] => 18601855 [patent_doc_number] => 20230276661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/144744 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18144744 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/144744
DISPLAY DEVICE May 7, 2023 Pending
Array ( [id] => 19560017 [patent_doc_number] => 20240371809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => STRUCTURE INCLUDING PASSIVE COMPONENT TRAVERSING MULTIPLE SEMICONDUCTOR CHIPS, WITH RELATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/311712 [patent_app_country] => US [patent_app_date] => 2023-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311712 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/311712
STRUCTURE INCLUDING PASSIVE COMPONENT TRAVERSING MULTIPLE SEMICONDUCTOR CHIPS, WITH RELATED METHODS AND SYSTEMS May 2, 2023 Pending
Array ( [id] => 19546528 [patent_doc_number] => 20240363564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR DEVICES WITH HYBRID BONDING LAYERS AND PROCESS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/309678 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309678 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/309678
SEMICONDUCTOR DEVICES WITH HYBRID BONDING LAYERS AND PROCESS OF MAKING THE SAME Apr 27, 2023 Pending
Array ( [id] => 19321533 [patent_doc_number] => 20240243080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => CAP LAYER FOR PAD OXIDATION PREVENTION [patent_app_type] => utility [patent_app_number] => 18/307165 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18307165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/307165
CAP LAYER FOR PAD OXIDATION PREVENTION Apr 25, 2023 Pending
Array ( [id] => 19376706 [patent_doc_number] => 12068286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Device with embedded high-bandwidth, high-capacity memory using wafer bonding [patent_app_type] => utility [patent_app_number] => 18/138270 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 12079 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138270 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/138270
Device with embedded high-bandwidth, high-capacity memory using wafer bonding Apr 23, 2023 Issued
Array ( [id] => 19110214 [patent_doc_number] => 11963347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => One-time programmable memory device including anti-fuse element [patent_app_type] => utility [patent_app_number] => 18/304834 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 46 [patent_no_of_words] => 8254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304834 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/304834
One-time programmable memory device including anti-fuse element Apr 20, 2023 Issued
Array ( [id] => 19161209 [patent_doc_number] => 20240153916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING MOLDED DIE STACK AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/304591 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304591 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/304591
SEMICONDUCTOR DEVICE INCLUDING MOLDED DIE STACK AND METHODS OF FORMING THE SAME Apr 20, 2023 Pending
Array ( [id] => 18821415 [patent_doc_number] => 20230395756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => INTERCONNECT STRUCTURES FOR IMPROVED LIGHT-EMITTING DIODE CHIP PERFORMANCE [patent_app_type] => utility [patent_app_number] => 18/302106 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/302106
INTERCONNECT STRUCTURES FOR IMPROVED LIGHT-EMITTING DIODE CHIP PERFORMANCE Apr 17, 2023 Pending
Array ( [id] => 18835339 [patent_doc_number] => 20230403866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/297266 [patent_app_country] => US [patent_app_date] => 2023-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18297266 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/297266
SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME Apr 6, 2023 Pending
Array ( [id] => 19161208 [patent_doc_number] => 20240153915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/297012 [patent_app_country] => US [patent_app_date] => 2023-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18297012 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/297012
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Apr 6, 2023 Pending
Array ( [id] => 19484189 [patent_doc_number] => 20240332231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => DIRECT HYBRID BONDING IN TOPOGRAPHIC PACKAGES [patent_app_type] => utility [patent_app_number] => 18/194591 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194591 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/194591
DIRECT HYBRID BONDING IN TOPOGRAPHIC PACKAGES Mar 30, 2023 Pending
Array ( [id] => 19356916 [patent_doc_number] => 12057373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Stackable fully molded semiconductor structure with through silicon via (TSV) vertical interconnects and method of making the same [patent_app_type] => utility [patent_app_number] => 18/126893 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 11776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126893 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/126893
Stackable fully molded semiconductor structure with through silicon via (TSV) vertical interconnects and method of making the same Mar 26, 2023 Issued
Array ( [id] => 18714798 [patent_doc_number] => 20230337443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => SRAM DEVICE AND 3D SEMICONDUCTOR INTEGRATED CIRCUIT THEREOF [patent_app_type] => utility [patent_app_number] => 18/126761 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126761 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/126761
SRAM device and 3D semiconductor integrated circuit thereof Mar 26, 2023 Issued
Array ( [id] => 18500585 [patent_doc_number] => 20230223380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => BONDED WAFER DEVICE STRUCTURE AND METHODS FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/124771 [patent_app_country] => US [patent_app_date] => 2023-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18124771 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/124771
Bonded wafer device structure and methods for making the same Mar 21, 2023 Issued
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