Search

Weilun Lo

Examiner (ID: 2971)

Most Active Art Unit
3402
Art Unit(s)
3748, 3761, 2179, 3402, 3723, 3747, 2899
Total Applications
2327
Issued Applications
2049
Pending Applications
47
Abandoned Applications
225

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16772964 [patent_doc_number] => 10984072 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-20 [patent_title] => Fast fourier transform (FFT) circuit with an integrated half-bin offset [patent_app_type] => utility [patent_app_number] => 16/280150 [patent_app_country] => US [patent_app_date] => 2019-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16280150 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/280150
Fast fourier transform (FFT) circuit with an integrated half-bin offset Feb 19, 2019 Issued
Array ( [id] => 16416506 [patent_doc_number] => 10824397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Random number generation [patent_app_type] => utility [patent_app_number] => 16/272343 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2499 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272343 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/272343
Random number generation Feb 10, 2019 Issued
Array ( [id] => 16241335 [patent_doc_number] => 20200258569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => MULTI-BIT DOT PRODUCT ENGINE [patent_app_type] => utility [patent_app_number] => 16/271811 [patent_app_country] => US [patent_app_date] => 2019-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16271811 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/271811
Multi-bit dot product engine Feb 8, 2019 Issued
Array ( [id] => 14379617 [patent_doc_number] => 20190163721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => EFFICIENT STORAGE OF APPROXIMATE ORDER STATISTICS OF REAL NUMBERS [patent_app_type] => utility [patent_app_number] => 16/264581 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16264581 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/264581
Efficient storage of approximate order statistics of real numbers Jan 30, 2019 Issued
Array ( [id] => 15936357 [patent_doc_number] => 20200159812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => COMPRESSION-ENCODING SCHEDULED INPUTS FOR MATRIX COMPUTATIONS [patent_app_type] => utility [patent_app_number] => 16/261199 [patent_app_country] => US [patent_app_date] => 2019-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16261199 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/261199
Compression-encoding scheduled inputs for matrix computations Jan 28, 2019 Issued
Array ( [id] => 16200580 [patent_doc_number] => 10725743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => System and method for generating random numbers [patent_app_type] => utility [patent_app_number] => 16/253062 [patent_app_country] => US [patent_app_date] => 2019-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2606 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16253062 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/253062
System and method for generating random numbers Jan 20, 2019 Issued
Array ( [id] => 18174057 [patent_doc_number] => 11573767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Calculation processor and calculation method for determining an exponential function [patent_app_type] => utility [patent_app_number] => 16/957979 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5020 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16957979 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/957979
Calculation processor and calculation method for determining an exponential function Jan 14, 2019 Issued
Array ( [id] => 15902811 [patent_doc_number] => 20200150925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => FPGA LOGIC CELL WITH IMPROVED SUPPORT FOR COUNTERS [patent_app_type] => utility [patent_app_number] => 16/242998 [patent_app_country] => US [patent_app_date] => 2019-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16242998 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/242998
FPGA logic cell with improved support for counters Jan 7, 2019 Issued
Array ( [id] => 16160559 [patent_doc_number] => 20200218512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => Decentralized Random Number Generator [patent_app_type] => utility [patent_app_number] => 16/242780 [patent_app_country] => US [patent_app_date] => 2019-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16242780 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/242780
Decentralized random number generator Jan 7, 2019 Issued
Array ( [id] => 16116247 [patent_doc_number] => 20200210146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => BINARY PARALLEL ADDER AND MULTIPLIER [patent_app_type] => utility [patent_app_number] => 16/237104 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237104 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237104
Binary parallel adder and multiplier Dec 30, 2018 Issued
Array ( [id] => 16116987 [patent_doc_number] => 20200210516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR FAST FOURIER TRANSFORM CONFIGURATION AND COMPUTATION INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/236464 [patent_app_country] => US [patent_app_date] => 2018-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236464 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236464
Apparatuses, methods, and systems for fast fourier transform configuration and computation instructions Dec 28, 2018 Issued
Array ( [id] => 15398969 [patent_doc_number] => 10540141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Method and apparatus for use in the design and manufacture of integrated circuits [patent_app_type] => utility [patent_app_number] => 16/229499 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 7771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229499 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/229499
Method and apparatus for use in the design and manufacture of integrated circuits Dec 20, 2018 Issued
Array ( [id] => 16675574 [patent_doc_number] => 20210064340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => ARITHMETIC CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/959986 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 523 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16959986 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/959986
Arithmetic circuit for performing product-sum arithmetic Dec 17, 2018 Issued
Array ( [id] => 18577435 [patent_doc_number] => 11733966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Protection system and method [patent_app_type] => utility [patent_app_number] => 16/954064 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10143 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16954064 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/954064
Protection system and method Dec 17, 2018 Issued
Array ( [id] => 14735443 [patent_doc_number] => 10387121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Apparatuses and methods for random number generation [patent_app_type] => utility [patent_app_number] => 16/213835 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 14768 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16213835 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/213835
Apparatuses and methods for random number generation Dec 6, 2018 Issued
Array ( [id] => 15998443 [patent_doc_number] => 20200175092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => Assessing Distances Between Pairs Of Histograms Based On Relaxed Flow Constraints [patent_app_type] => utility [patent_app_number] => 16/208990 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208990 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/208990
Assessing distances between pairs of histograms based on relaxed flow constraints Dec 3, 2018 Issued
Array ( [id] => 14047253 [patent_doc_number] => 20190079733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => ASCII-SEEDED RANDOM NUMBER GENERATOR [patent_app_type] => utility [patent_app_number] => 16/188261 [patent_app_country] => US [patent_app_date] => 2018-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16188261 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/188261
ASCII-seeded random number generator Nov 11, 2018 Issued
Array ( [id] => 16408710 [patent_doc_number] => 10817262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Reduced and pipelined hardware architecture for Montgomery Modular Multiplication [patent_app_type] => utility [patent_app_number] => 16/184139 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6135 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184139
Reduced and pipelined hardware architecture for Montgomery Modular Multiplication Nov 7, 2018 Issued
Array ( [id] => 16285235 [patent_doc_number] => 20200278837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => ADDITION METHOD, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/649948 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16649948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/649948
Addition method, semiconductor device, and electronic device Nov 4, 2018 Issued
Array ( [id] => 16309376 [patent_doc_number] => 10778192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Filter coefficient calculation device, signal generation device including the same, filter coefficient calculation method, and signal generation method [patent_app_type] => utility [patent_app_number] => 16/166738 [patent_app_country] => US [patent_app_date] => 2018-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6295 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16166738 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/166738
Filter coefficient calculation device, signal generation device including the same, filter coefficient calculation method, and signal generation method Oct 21, 2018 Issued
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