Search

Weilun Lo

Examiner (ID: 2971)

Most Active Art Unit
3402
Art Unit(s)
3748, 3761, 2179, 3402, 3723, 3747, 2899
Total Applications
2327
Issued Applications
2049
Pending Applications
47
Abandoned Applications
225

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18415044 [patent_doc_number] => 11669587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Synthetic scaling applied to shared neural networks [patent_app_type] => utility [patent_app_number] => 17/742245 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 63 [patent_no_of_words] => 30232 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17742245 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/742245
Synthetic scaling applied to shared neural networks May 10, 2022 Issued
Array ( [id] => 18839354 [patent_doc_number] => 11847428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Execution unit for evaluating functions using Newton Raphson iterations [patent_app_type] => utility [patent_app_number] => 17/660688 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 15841 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17660688 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/660688
Execution unit for evaluating functions using Newton Raphson iterations Apr 25, 2022 Issued
Array ( [id] => 18982502 [patent_doc_number] => 11907680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Multiplication and accumulation (MAC) operator [patent_app_type] => utility [patent_app_number] => 17/724253 [patent_app_country] => US [patent_app_date] => 2022-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 137 [patent_figures_cnt] => 137 [patent_no_of_words] => 92113 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17724253 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/724253
Multiplication and accumulation (MAC) operator Apr 18, 2022 Issued
Array ( [id] => 18446202 [patent_doc_number] => 11681774 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-20 [patent_title] => Classically-boosted quantum optimization [patent_app_type] => utility [patent_app_number] => 17/702244 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 17485 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702244 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/702244
Classically-boosted quantum optimization Mar 22, 2022 Issued
Array ( [id] => 18622245 [patent_doc_number] => 11755285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Semiconductor device including multiplier circuit [patent_app_type] => utility [patent_app_number] => 17/673932 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 52 [patent_no_of_words] => 29613 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673932 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/673932
Semiconductor device including multiplier circuit Feb 16, 2022 Issued
Array ( [id] => 18370619 [patent_doc_number] => 11650792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Multiple mode arithmetic circuit [patent_app_type] => utility [patent_app_number] => 17/569801 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569801 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569801
Multiple mode arithmetic circuit Jan 5, 2022 Issued
Array ( [id] => 17861856 [patent_doc_number] => 11443014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-13 [patent_title] => Sparse matrix multiplier in hardware and a reconfigurable data processor including same [patent_app_type] => utility [patent_app_number] => 17/520290 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 19020 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520290 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520290
Sparse matrix multiplier in hardware and a reconfigurable data processor including same Nov 4, 2021 Issued
Array ( [id] => 19356013 [patent_doc_number] => 12056461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Integrated circuits with machine learning extensions [patent_app_type] => utility [patent_app_number] => 17/484845 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6556 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484845 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/484845
Integrated circuits with machine learning extensions Sep 23, 2021 Issued
Array ( [id] => 17372380 [patent_doc_number] => 20220027432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR DENSE/SPARSE LINEAR SYSTEM SOLVER ACCELERATOR [patent_app_type] => utility [patent_app_number] => 17/482995 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482995 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482995
SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR DENSE/SPARSE LINEAR SYSTEM SOLVER ACCELERATOR Sep 22, 2021 Pending
Array ( [id] => 17338030 [patent_doc_number] => 20220004361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => REPURPOSED HEXADECIMAL FLOATING POINT DATA PATH [patent_app_type] => utility [patent_app_number] => 17/480180 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480180 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480180
Repurposed hexadecimal floating point data path Sep 20, 2021 Issued
Array ( [id] => 17276494 [patent_doc_number] => 20210382692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => PROCESSING-IN-MEMORY (PIM) DEVICES AND METHODS OF TESTING THE PIM DEVICES [patent_app_type] => utility [patent_app_number] => 17/407540 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407540 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407540
Processing-in-memory (PIM) devices and methods of testing the PIM devices Aug 19, 2021 Issued
Array ( [id] => 17430282 [patent_doc_number] => 20220057991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => Combinatorial Logic Circuits With Feedback [patent_app_type] => utility [patent_app_number] => 17/400937 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400937
Combinatorial logic circuits with feedback Aug 11, 2021 Issued
Array ( [id] => 17478295 [patent_doc_number] => 20220085799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => Filter and Method with Multiplication Operation Approximation Capability [patent_app_type] => utility [patent_app_number] => 17/399071 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399071 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399071
Filter and method with multiplication operation approximation capability Aug 10, 2021 Issued
Array ( [id] => 17445993 [patent_doc_number] => 20220066498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => HIGH THROUGHPUT LINEAR FEEDBACK SHIFT REGISTER [patent_app_type] => utility [patent_app_number] => 17/393492 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393492
HIGH THROUGHPUT LINEAR FEEDBACK SHIFT REGISTER Aug 3, 2021 Pending
Array ( [id] => 17915574 [patent_doc_number] => 20220317970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => PERIPHERAL TOOLDUAL/QUAD-FRACTURABLE DIGITAL SIGNAL PROCESSING BLOCK FOR PROGRAMMABLE GATE ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 17/389128 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389128 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389128
PERIPHERAL TOOLDUAL/QUAD-FRACTURABLE DIGITAL SIGNAL PROCESSING BLOCK FOR PROGRAMMABLE GATE ARCHITECTURES Jul 28, 2021 Pending
Array ( [id] => 18547292 [patent_doc_number] => 11720645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Optimization problem solving calculation apparatus [patent_app_type] => utility [patent_app_number] => 17/363872 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 16160 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 386 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17363872 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/363872
Optimization problem solving calculation apparatus Jun 29, 2021 Issued
Array ( [id] => 18766046 [patent_doc_number] => 11816449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Low-loss arithmetic circuit and operating method of the same [patent_app_type] => utility [patent_app_number] => 17/356743 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4633 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17356743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/356743
Low-loss arithmetic circuit and operating method of the same Jun 23, 2021 Issued
Array ( [id] => 17252811 [patent_doc_number] => 11188300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-30 [patent_title] => Preparation and execution of quantized scaling on integrated circuitry [patent_app_type] => utility [patent_app_number] => 17/351250 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 8750 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351250 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351250
Preparation and execution of quantized scaling on integrated circuitry Jun 17, 2021 Issued
Array ( [id] => 18463448 [patent_doc_number] => 11687738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Chopper stabilized bias unit element with binary weighted charge transfer capacitors [patent_app_type] => utility [patent_app_number] => 17/334899 [patent_app_country] => US [patent_app_date] => 2021-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 8213 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334899
Chopper stabilized bias unit element with binary weighted charge transfer capacitors May 30, 2021 Issued
Array ( [id] => 17069234 [patent_doc_number] => 20210271450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => PROCESSING CORE WITH DATA ASSOCIATIVE ADAPTIVE ROUNDING [patent_app_type] => utility [patent_app_number] => 17/321925 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/321925
Processing core with data associative adaptive rounding May 16, 2021 Issued
Menu