Weilun Lo

Array ( [id] => 16675573 [patent_doc_number] => 20210064339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => ARITHMETIC CIRCUIT, AND NEURAL PROCESSING UNIT AND ELECTRONIC APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/847872 [patent_app_country] => US [patent_app_date] => 2020-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16193074 [patent_doc_number] => 20200233923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => BINARY, TERNARY AND BIT SERIAL COMPUTE-IN-MEMORY CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/839013 [patent_app_country] => US [patent_app_date] => 2020-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16839013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18119155 [patent_doc_number] => 11550548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Autonomous pseudo-random seed generator for computing devices [patent_app_type] => utility [patent_app_number] => 16/836841 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 28764 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18445929 [patent_doc_number] => 11681498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Neural network arithmetic processing device and neural network arithmetic processing method [patent_app_type] => utility [patent_app_number] => 16/819303 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9818 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16819303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16535154 [patent_doc_number] => 10877754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Matrix computation engine [patent_app_type] => utility [patent_app_number] => 16/818200 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6343 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17069235 [patent_doc_number] => 20210271451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => MAPPING CONVOLUTION TO A PARTITION CHANNEL CONVOLUTION ENGINE [patent_app_type] => utility [patent_app_number] => 16/805339 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16737569 [patent_doc_number] => 10963221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Efficient FPGA multipliers [patent_app_type] => utility [patent_app_number] => 16/802966 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6899 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16802966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17061830 [patent_doc_number] => 11106431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Apparatus and method of fast floating-point adder tree for neural networks [patent_app_type] => utility [patent_app_number] => 16/798300 [patent_app_country] => US [patent_app_date] => 2020-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6135 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16798300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16698570 [patent_doc_number] => 10949167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Error bounded multiplication by invariant rationals [patent_app_type] => utility [patent_app_number] => 16/796786 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8996 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17940338 [patent_doc_number] => 11474791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Method and apparatus for efficient multiplication to improve performance in computational machines [patent_app_type] => utility [patent_app_number] => 16/790614 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 33 [patent_no_of_words] => 12345 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16790614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16002589 [patent_doc_number] => 20200177165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => SCALABLE FIR FILTER [patent_app_type] => utility [patent_app_number] => 16/788814 [patent_app_country] => US [patent_app_date] => 2020-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16801983 [patent_doc_number] => 10996926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Variable precision floating-point multiplier [patent_app_type] => utility [patent_app_number] => 16/785933 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 7056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16208851 [patent_doc_number] => 20200241841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => RANDOM NUMBER GENERATING CIRCUIT AND SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 16/734457 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16185962 [patent_doc_number] => 10719294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Hardware sort accelerator sharing first level processor cache [patent_app_type] => utility [patent_app_number] => 16/718419 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8769 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16718419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16263188 [patent_doc_number] => 10754620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Self-timed random number generator [patent_app_type] => utility [patent_app_number] => 16/707349 [patent_app_country] => US [patent_app_date] => 2019-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16707349 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18606596 [patent_doc_number] => 11748060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Method and apparatus for use in the design and manufacture of integrated circuits [patent_app_type] => utility [patent_app_number] => 16/694915 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 7694 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17589765 [patent_doc_number] => 11328038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Computational units for batch normalization [patent_app_type] => utility [patent_app_number] => 16/695138 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11724 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17338265 [patent_doc_number] => 20220004596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => Inverse Matrix Calculation Device and Inverse Matrix Calculation Processing Method [patent_app_type] => utility [patent_app_number] => 17/296716 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17296716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16652323 [patent_doc_number] => 10929504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Bit matrix multiplication [patent_app_type] => utility [patent_app_number] => 16/691327 [patent_app_country] => US [patent_app_date] => 2019-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 19300 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16691327 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15935719 [patent_doc_number] => 20200159493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => BLOCK FLOATING POINT FOR NEURAL NETWORK IMPLEMENTATIONS [patent_app_type] => utility [patent_app_number] => 16/689907 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689907 [rel_patent_id] =>[rel_patent_doc_number] =>)