Search

Weilun Lo

Examiner (ID: 2971)

Most Active Art Unit
3402
Art Unit(s)
3748, 3761, 2179, 3402, 3723, 3747, 2899
Total Applications
2327
Issued Applications
2049
Pending Applications
47
Abandoned Applications
225

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16630329 [patent_doc_number] => 20210048982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => PARTIAL PRODUCT FLOATING-POINT MULTIPLICATION CIRCUITRY OPERAND SUMMATION [patent_app_type] => utility [patent_app_number] => 16/538985 [patent_app_country] => US [patent_app_date] => 2019-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16538985 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/538985
PARTIAL PRODUCT FLOATING-POINT MULTIPLICATION CIRCUITRY OPERAND SUMMATION Aug 12, 2019 Abandoned
Array ( [id] => 17423022 [patent_doc_number] => 11256476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Multiple mode arithmetic circuit [patent_app_type] => utility [patent_app_number] => 16/535878 [patent_app_country] => US [patent_app_date] => 2019-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16535878 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/535878
Multiple mode arithmetic circuit Aug 7, 2019 Issued
Array ( [id] => 16130431 [patent_doc_number] => 10698976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Low latency matrix multiply unit [patent_app_type] => utility [patent_app_number] => 16/529662 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11246 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529662 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/529662
Low latency matrix multiply unit Jul 31, 2019 Issued
Array ( [id] => 17394729 [patent_doc_number] => 11243743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Optimization of neural networks using hardware calculation efficiency and adjustment factors [patent_app_type] => utility [patent_app_number] => 16/528982 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528982 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528982
Optimization of neural networks using hardware calculation efficiency and adjustment factors Jul 31, 2019 Issued
Array ( [id] => 17252810 [patent_doc_number] => 11188299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Repurposed hexadecimal floating point data path [patent_app_type] => utility [patent_app_number] => 16/527138 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3949 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527138 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/527138
Repurposed hexadecimal floating point data path Jul 30, 2019 Issued
Array ( [id] => 18356696 [patent_doc_number] => 11645096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Computer architecture for performing multiplication using correlithm objects in a correlithm object processing system [patent_app_type] => utility [patent_app_number] => 16/521416 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 33 [patent_no_of_words] => 34780 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521416 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521416
Computer architecture for performing multiplication using correlithm objects in a correlithm object processing system Jul 23, 2019 Issued
Array ( [id] => 16584713 [patent_doc_number] => 20210019115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SYSTEM AND METHOD FOR SUPPORTING ALTERNATE NUMBER FORMAT FOR EFFICIENT MULTIPLICATION [patent_app_type] => utility [patent_app_number] => 16/511085 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/511085
System and method for supporting alternate number format for efficient multiplication Jul 14, 2019 Issued
Array ( [id] => 17187449 [patent_doc_number] => 20210334334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => TWIDDLE FACTOR GENERATING CIRCUIT FOR AN NTT PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/259065 [patent_app_country] => US [patent_app_date] => 2019-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17259065 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/259065
TWIDDLE FACTOR GENERATING CIRCUIT FOR AN NTT PROCESSOR Jul 8, 2019 Pending
Array ( [id] => 17263851 [patent_doc_number] => 20210376836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SIGNAL PROCESSING CIRCUIT, SIGNAL PROCESSING DEVICE, AND SIGNAL PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/250310 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17250310 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/250310
SIGNAL PROCESSING CIRCUIT, SIGNAL PROCESSING DEVICE, AND SIGNAL PROCESSING METHOD Jul 4, 2019 Pending
Array ( [id] => 17069237 [patent_doc_number] => 20210271453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => ARITHMETIC LOGIC UNIT, MULTIPLY-ACCUMULATE OPERATION DEVICE, MULTIPLY-ACCUMULATE OPERATION CIRCUIT, AND MULTIPLY-ACCUMULATE OPERATION SYSTEM [patent_app_type] => utility [patent_app_number] => 17/258309 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17258309 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/258309
Arithmetic logic unit, multiply-accumulate operation device, multiply-accumulate operation circuit, and multiply-accumulate operation system Jul 4, 2019 Issued
Array ( [id] => 16543943 [patent_doc_number] => 20200410358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => EFFICIENT ARTIFICIAL INTELLIGENCE ACCELERATOR [patent_app_type] => utility [patent_app_number] => 16/457512 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457512 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/457512
EFFICIENT ARTIFICIAL INTELLIGENCE ACCELERATOR Jun 27, 2019 Abandoned
Array ( [id] => 15027435 [patent_doc_number] => 20190324722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => VARIABLE PRECISION FLOATING-POINT MULTIPLIER [patent_app_type] => utility [patent_app_number] => 16/451759 [patent_app_country] => US [patent_app_date] => 2019-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16451759 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/451759
Variable precision floating-point multiplier Jun 24, 2019 Issued
Array ( [id] => 16529732 [patent_doc_number] => 20200403813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => METHOD AND APPARATUS TO PROVIDE MEMORY BASED PHYSICALLY UNCLONABLE FUNCTIONS [patent_app_type] => utility [patent_app_number] => 16/447887 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447887 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447887
Method and apparatus to provide memory based physically unclonable functions Jun 19, 2019 Issued
Array ( [id] => 15903437 [patent_doc_number] => 20200151238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => Processor and Methods Configured to Provide a Low-Complexity Input/Output Pruning Fast Fourier Transform [patent_app_type] => utility [patent_app_number] => 16/444946 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444946 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/444946
Processor and Methods Configured to Provide a Low-Complexity Input/Output Pruning Fast Fourier Transform Jun 17, 2019 Abandoned
Array ( [id] => 16514994 [patent_doc_number] => 20200394252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => INTEGRATOR VOLTAGE SHIFTING FOR IMPROVED PERFORMANCE IN SOFTMAX OPERATION [patent_app_type] => utility [patent_app_number] => 16/439246 [patent_app_country] => US [patent_app_date] => 2019-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16439246 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/439246
Integrator voltage shifting for improved performance in softmax operation Jun 11, 2019 Issued
Array ( [id] => 17091545 [patent_doc_number] => 11119733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Execution unit configured to evaluate functions using at least one multiplier circuit [patent_app_type] => utility [patent_app_number] => 16/427828 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 16715 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16427828 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/427828
Execution unit configured to evaluate functions using at least one multiplier circuit May 30, 2019 Issued
Array ( [id] => 15638491 [patent_doc_number] => 10592239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Matrix computation engine [patent_app_type] => utility [patent_app_number] => 16/423702 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6320 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423702 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/423702
Matrix computation engine May 27, 2019 Issued
Array ( [id] => 16470212 [patent_doc_number] => 20200371749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => MULTIPLIER CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/417866 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/417866
Multiplier circuit May 20, 2019 Issued
Array ( [id] => 17715564 [patent_doc_number] => 11379556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Apparatus and method for matrix operations [patent_app_type] => utility [patent_app_number] => 16/417937 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8195 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417937 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/417937
Apparatus and method for matrix operations May 20, 2019 Issued
Array ( [id] => 14782643 [patent_doc_number] => 20190266219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => TECHNOLOGIES FOR PERFORMING MACRO OPERATIONS IN MEMORY [patent_app_type] => utility [patent_app_number] => 16/411730 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411730 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411730
Technologies for performing macro operations in memory May 13, 2019 Issued
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