Search

Wensing W. Kuo

Examiner (ID: 17009)

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
470
Issued Applications
358
Pending Applications
5
Abandoned Applications
110

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8969240 [patent_doc_number] => 08508056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-13 [patent_title] => 'Heat releasing semiconductor package, method for manufacturing the same, and display apparatus including the same' [patent_app_type] => utility [patent_app_number] => 12/813229 [patent_app_country] => US [patent_app_date] => 2010-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4812 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12813229 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/813229
Heat releasing semiconductor package, method for manufacturing the same, and display apparatus including the same Jun 9, 2010 Issued
Array ( [id] => 8122885 [patent_doc_number] => 20120085986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT-EMITTING DIODE' [patent_app_type] => utility [patent_app_number] => 13/321923 [patent_app_country] => US [patent_app_date] => 2010-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11971 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20120085986.pdf [firstpage_image] =>[orig_patent_app_number] => 13321923 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/321923
GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT-EMITTING DIODE Jun 8, 2010 Abandoned
Array ( [id] => 8528319 [patent_doc_number] => 08304892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Semiconductor package having substrate with solder ball connections and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/794027 [patent_app_country] => US [patent_app_date] => 2010-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 5442 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12794027 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/794027
Semiconductor package having substrate with solder ball connections and method of fabricating the same Jun 3, 2010 Issued
Array ( [id] => 6072939 [patent_doc_number] => 20110139230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'ION IMPLANTED SELECTIVE EMITTER SOLAR CELLS WITH IN SITU SURFACE PASSIVATION' [patent_app_type] => utility [patent_app_number] => 12/793363 [patent_app_country] => US [patent_app_date] => 2010-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20110139230.pdf [firstpage_image] =>[orig_patent_app_number] => 12793363 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/793363
Ion implanted selective emitter solar cells with in situ surface passivation Jun 2, 2010 Issued
Array ( [id] => 7977343 [patent_doc_number] => 08071418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Selective emitter solar cells formed by a hybrid diffusion and ion implantation process' [patent_app_type] => utility [patent_app_number] => 12/793334 [patent_app_country] => US [patent_app_date] => 2010-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8700 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/071/08071418.pdf [firstpage_image] =>[orig_patent_app_number] => 12793334 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/793334
Selective emitter solar cells formed by a hybrid diffusion and ion implantation process Jun 2, 2010 Issued
Array ( [id] => 6295073 [patent_doc_number] => 20100240175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'METHOD FOR MAKING A STACKED PACKAGE SEMICONDUCTOR MODULE HAVING PACKAGES STACKED IN A CAVITY IN THE MODULE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/784434 [patent_app_country] => US [patent_app_date] => 2010-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6981 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20100240175.pdf [firstpage_image] =>[orig_patent_app_number] => 12784434 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/784434
Method for making a stacked package semiconductor module having packages stacked in a cavity in the module substrate May 19, 2010 Issued
Array ( [id] => 6469806 [patent_doc_number] => 20100207099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND FABRICATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/770534 [patent_app_country] => US [patent_app_date] => 2010-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4193 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20100207099.pdf [firstpage_image] =>[orig_patent_app_number] => 12770534 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/770534
Nitride semiconductor light emitting device and fabricating method thereof Apr 28, 2010 Issued
Array ( [id] => 7506795 [patent_doc_number] => 20110254138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'LOW-TEMPERATURE ABSORBER FILM AND METHOD OF FABRICATION' [patent_app_type] => utility [patent_app_number] => 12/760620 [patent_app_country] => US [patent_app_date] => 2010-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7103 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20110254138.pdf [firstpage_image] =>[orig_patent_app_number] => 12760620 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/760620
LOW-TEMPERATURE ABSORBER FILM AND METHOD OF FABRICATION Apr 14, 2010 Abandoned
Array ( [id] => 7506691 [patent_doc_number] => 20110254090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER' [patent_app_type] => utility [patent_app_number] => 12/760250 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3524 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20110254090.pdf [firstpage_image] =>[orig_patent_app_number] => 12760250 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/760250
Raised source/drain structure for enhanced strain coupling from stress liner Apr 13, 2010 Issued
Array ( [id] => 7506674 [patent_doc_number] => 20110254080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'TUNNEL FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/760287 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4590 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20110254080.pdf [firstpage_image] =>[orig_patent_app_number] => 12760287 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/760287
Tunnel field effect transistor Apr 13, 2010 Issued
Array ( [id] => 6010580 [patent_doc_number] => 20110220977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'SEMICONDUCTOR DEVICES WITH BURIED BIT LINES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 12/760140 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12080 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20110220977.pdf [firstpage_image] =>[orig_patent_app_number] => 12760140 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/760140
Semiconductor devices with buried bit lines and methods of manufacturing semiconductor devices Apr 13, 2010 Issued
Array ( [id] => 9113662 [patent_doc_number] => 08569841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel' [patent_app_type] => utility [patent_app_number] => 12/754147 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 54 [patent_no_of_words] => 22231 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 649 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12754147 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754147
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel Apr 4, 2010 Issued
Array ( [id] => 9100192 [patent_doc_number] => 08564071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact' [patent_app_type] => utility [patent_app_number] => 12/754061 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 211 [patent_figures_cnt] => 212 [patent_no_of_words] => 31153 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 882 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12754061 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754061
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact Apr 4, 2010 Issued
Array ( [id] => 9127755 [patent_doc_number] => 08575706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode' [patent_app_type] => utility [patent_app_number] => 12/754091 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 211 [patent_figures_cnt] => 212 [patent_no_of_words] => 31202 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 878 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12754091 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754091
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode Apr 4, 2010 Issued
Array ( [id] => 6286140 [patent_doc_number] => 20100237430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'Channelized Gate Level Cross-Coupled Transistor Device with Equal Width PMOS Transistors and Equal Width NMOS Transistors' [patent_app_type] => utility [patent_app_number] => 12/754129 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 19512 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20100237430.pdf [firstpage_image] =>[orig_patent_app_number] => 12754129 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754129
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer Apr 4, 2010 Issued
Array ( [id] => 9113662 [patent_doc_number] => 08569841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel' [patent_app_type] => utility [patent_app_number] => 12/754147 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 54 [patent_no_of_words] => 22231 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 649 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12754147 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754147
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel Apr 4, 2010 Issued
Array ( [id] => 9086893 [patent_doc_number] => 08558322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature' [patent_app_type] => utility [patent_app_number] => 12/754114 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 211 [patent_figures_cnt] => 192 [patent_no_of_words] => 31219 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 697 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12754114 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754114
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature Apr 4, 2010 Issued
Array ( [id] => 6264201 [patent_doc_number] => 20100252893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'Channelized Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Three Gate Electrode Tracks with Crossing Gate Electrode Connections' [patent_app_type] => utility [patent_app_number] => 12/754384 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 19416 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20100252893.pdf [firstpage_image] =>[orig_patent_app_number] => 12754384 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754384
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors Apr 4, 2010 Issued
Array ( [id] => 8702001 [patent_doc_number] => 08395224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes' [patent_app_type] => utility [patent_app_number] => 12/753758 [patent_app_country] => US [patent_app_date] => 2010-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 49 [patent_no_of_words] => 20450 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 762 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12753758 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/753758
Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes Apr 1, 2010 Issued
Array ( [id] => 7540847 [patent_doc_number] => 08058691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Semiconductor device including cross-coupled transistors formed from linear-shaped gate level features' [patent_app_type] => utility [patent_app_number] => 12/753817 [patent_app_country] => US [patent_app_date] => 2010-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 45 [patent_no_of_words] => 19383 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/058/08058691.pdf [firstpage_image] =>[orig_patent_app_number] => 12753817 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/753817
Semiconductor device including cross-coupled transistors formed from linear-shaped gate level features Apr 1, 2010 Issued
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