Search

William A. Harriston

Examiner (ID: 9215, Phone: (571)270-3897 , Office: P/2899 )

Most Active Art Unit
2899
Art Unit(s)
2899, 2826, 4146, 2896
Total Applications
1240
Issued Applications
1069
Pending Applications
77
Abandoned Applications
116

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18890998 [patent_doc_number] => 11869775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Semiconductor packages [patent_app_type] => utility [patent_app_number] => 18/169161 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169161 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/169161
Semiconductor packages Feb 13, 2023 Issued
Array ( [id] => 18789385 [patent_doc_number] => 20230378044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => FLIP-CHIP BONDING STRUCTURE AND SUBSTRATE THEREOF [patent_app_type] => utility [patent_app_number] => 18/109337 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109337 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109337
Flip-chip bonding structure and substrate thereof Feb 13, 2023 Issued
Array ( [id] => 20720308 [patent_doc_number] => 12635581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Package structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/167095 [patent_app_country] => US [patent_app_date] => 2023-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 3326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18167095 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/167095
Package structure and method for forming the same Feb 9, 2023 Issued
Array ( [id] => 18440097 [patent_doc_number] => 20230187392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => Redistribution Layers And Methods Of Fabricating The Same In Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/166960 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166960 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166960
Redistribution layers and methods of fabricating the same in semiconductor devices Feb 8, 2023 Issued
Array ( [id] => 19494269 [patent_doc_number] => 12112992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Package having an electronic component and an encapsulant encapsulating a dielectric layer and a semiconductor die of the electronic component [patent_app_type] => utility [patent_app_number] => 18/107800 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 7354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18107800 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/107800
Package having an electronic component and an encapsulant encapsulating a dielectric layer and a semiconductor die of the electronic component Feb 8, 2023 Issued
Array ( [id] => 19364314 [patent_doc_number] => 20240266348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => FLIP-CHIP FIELD EFFECT TRANSISTOR LAYOUTS AND STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/105586 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105586 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105586
FLIP-CHIP FIELD EFFECT TRANSISTOR LAYOUTS AND STRUCTURES Feb 2, 2023 Pending
Array ( [id] => 18394926 [patent_doc_number] => 20230163147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => METHOD OF MANUFACTURING PACKAGE UNIT, PACKAGE UNIT, ELECTRONIC MODULE, AND EQUIPMENT [patent_app_type] => utility [patent_app_number] => 18/159132 [patent_app_country] => US [patent_app_date] => 2023-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18159132 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/159132
Method of manufacturing package unit, package unit, electronic module, and equipment Jan 24, 2023 Issued
Array ( [id] => 18379809 [patent_doc_number] => 20230154898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => 3DIC STRUCTURE AND METHODS OF FORMING [patent_app_type] => utility [patent_app_number] => 18/156848 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156848 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/156848
3DIC structure and methods of forming Jan 18, 2023 Issued
Array ( [id] => 19812388 [patent_doc_number] => 12243801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Substrates for semiconductor device assemblies and systems with improved thermal performance and methods for making the same [patent_app_type] => utility [patent_app_number] => 18/154615 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5220 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154615 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154615
Substrates for semiconductor device assemblies and systems with improved thermal performance and methods for making the same Jan 12, 2023 Issued
Array ( [id] => 19305760 [patent_doc_number] => 20240234340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => INTEGRATED CIRCUIT PACKAGES AND METHODS [patent_app_type] => utility [patent_app_number] => 18/151545 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151545 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151545
Integrated circuit packages and methods Jan 8, 2023 Issued
Array ( [id] => 18366600 [patent_doc_number] => 20230148191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/094794 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094794 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/094794
Semiconductor package Jan 8, 2023 Issued
Array ( [id] => 19285752 [patent_doc_number] => 20240222229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => BACK SIDE CONTACTS FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/091997 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/091997
BACK SIDE CONTACTS FOR SEMICONDUCTOR DEVICES Dec 29, 2022 Pending
Array ( [id] => 20612936 [patent_doc_number] => 12588558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 18/069318 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2095 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18069318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/069318
Semiconductor package Dec 20, 2022 Issued
Array ( [id] => 18360793 [patent_doc_number] => 20230142384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => FULLY MOLDED BRIDGE INTERPOSER AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/085397 [patent_app_country] => US [patent_app_date] => 2022-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18085397 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/085397
Fully molded bridge interposer and method of making the same Dec 19, 2022 Issued
Array ( [id] => 18318944 [patent_doc_number] => 20230117072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/066487 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066487 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/066487
Integrated circuit device and semiconductor package including the same Dec 14, 2022 Issued
Array ( [id] => 20566235 [patent_doc_number] => 12568862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Stacked semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 18/078096 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18078096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/078096
Stacked semiconductor device and method of fabricating the same Dec 8, 2022 Issued
Array ( [id] => 20229327 [patent_doc_number] => 12417983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 18/063413 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063413 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063413
Semiconductor package Dec 7, 2022 Issued
Array ( [id] => 19376596 [patent_doc_number] => 12068176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Apparatus and method of manufacturing solder bump [patent_app_type] => utility [patent_app_number] => 18/063029 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7173 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063029
Apparatus and method of manufacturing solder bump Dec 6, 2022 Issued
Array ( [id] => 18935513 [patent_doc_number] => 11887957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/076529 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 13477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18076529 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/076529
Semiconductor device Dec 6, 2022 Issued
Array ( [id] => 20626165 [patent_doc_number] => 12593695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Structure and process for warpage reduction [patent_app_type] => utility [patent_app_number] => 18/060574 [patent_app_country] => US [patent_app_date] => 2022-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18060574 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/060574
Structure and process for warpage reduction Nov 30, 2022 Issued
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