| Application number | Title of the application | Filing Date | Status |
|---|
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| 08/079787 | DATA BUS INTERFACE APPARATUS | Jun 22, 1993 | Pending |
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| 08/058848 | DUAL MODE AMPLIFIER NETWORK | May 9, 1993 | Pending |
Array
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Array
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[patent_issue_date] => 1995-08-08
[patent_title] => 'Method and apparatus for estimating maximum likelihood sequence in digital communication receiver with reduced real time calculations'
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| 08/034817 | FIXED EQUALIZER AND EQUALIZING METHOD | Mar 18, 1993 | Pending |
Array
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[id] => 3500169
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| 08/025437 | SYNCHRONIZING SYSTEM FOR A SIGNAL HAVING DISTRIBUTED FRAME PATTERNS | Mar 2, 1993 | Abandoned |
Array
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| 08/016098 | DIGITAL SIGNAL PROCESSING CIRCUIT | Feb 9, 1993 | Abandoned |
| 08/012708 | SYNCHRONOUS SYSTEM PERMITTING TO CONTROL MODEMS CONNECTED THERETO AND MODEMS SUITABLE FOR SUCH A SYSTEM | Feb 2, 1993 | Abandoned |
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