Search

William A. Luther

Examiner (ID: 14002)

Most Active Art Unit
2731
Art Unit(s)
2616, 2667, 2614, 2607, 2731, 2664
Total Applications
411
Issued Applications
321
Pending Applications
46
Abandoned Applications
44

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1160822 [patent_doc_number] => 06775684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Digital matched filter' [patent_app_type] => B1 [patent_app_number] => 09/586596 [patent_app_country] => US [patent_app_date] => 2000-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5291 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775684.pdf [firstpage_image] =>[orig_patent_app_number] => 09586596 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/586596
Digital matched filter Jun 1, 2000 Issued
Array ( [id] => 1278922 [patent_doc_number] => 06654776 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method and apparatus for computing parallel leading zero count with offset' [patent_app_type] => B1 [patent_app_number] => 09/587176 [patent_app_country] => US [patent_app_date] => 2000-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6455 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654776.pdf [firstpage_image] =>[orig_patent_app_number] => 09587176 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/587176
Method and apparatus for computing parallel leading zero count with offset Jun 1, 2000 Issued
Array ( [id] => 1310739 [patent_doc_number] => 06625633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Divider and method with high radix' [patent_app_type] => B1 [patent_app_number] => 09/585894 [patent_app_country] => US [patent_app_date] => 2000-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10772 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625633.pdf [firstpage_image] =>[orig_patent_app_number] => 09585894 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/585894
Divider and method with high radix May 31, 2000 Issued
Array ( [id] => 1164709 [patent_doc_number] => 06772187 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Parallel greater than analysis method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/586657 [patent_app_country] => US [patent_app_date] => 2000-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2961 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772187.pdf [firstpage_image] =>[orig_patent_app_number] => 09586657 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/586657
Parallel greater than analysis method and apparatus May 31, 2000 Issued
Array ( [id] => 1217981 [patent_doc_number] => 06711603 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Fractional, arithmetic unit, fractional arithmetic method, set-up engine for handling graphic images and computer-readable medium' [patent_app_type] => B1 [patent_app_number] => 09/583574 [patent_app_country] => US [patent_app_date] => 2000-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7296 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711603.pdf [firstpage_image] =>[orig_patent_app_number] => 09583574 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/583574
Fractional, arithmetic unit, fractional arithmetic method, set-up engine for handling graphic images and computer-readable medium May 30, 2000 Issued
Array ( [id] => 1186588 [patent_doc_number] => 06738795 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'Self-timed transmission system and method for processing multiple data sets' [patent_app_type] => B1 [patent_app_number] => 09/583206 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738795.pdf [firstpage_image] =>[orig_patent_app_number] => 09583206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/583206
Self-timed transmission system and method for processing multiple data sets May 29, 2000 Issued
Array ( [id] => 782079 [patent_doc_number] => 06996596 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-07 [patent_title] => 'Floating-point processor with operating mode having improved accuracy and high performance' [patent_app_type] => utility [patent_app_number] => 09/577238 [patent_app_country] => US [patent_app_date] => 2000-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 10651 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/996/06996596.pdf [firstpage_image] =>[orig_patent_app_number] => 09577238 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/577238
Floating-point processor with operating mode having improved accuracy and high performance May 22, 2000 Issued
Array ( [id] => 662470 [patent_doc_number] => 07107302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-12 [patent_title] => 'Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units' [patent_app_type] => utility [patent_app_number] => 09/570847 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 9658 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/107/07107302.pdf [firstpage_image] =>[orig_patent_app_number] => 09570847 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/570847
Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units May 11, 2000 Issued
Array ( [id] => 321008 [patent_doc_number] => 07523151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-21 [patent_title] => 'Method and apparatus for performing computations using residue arithmetic' [patent_app_type] => utility [patent_app_number] => 09/569944 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 7049 [patent_no_of_claims] => 84 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523151.pdf [firstpage_image] =>[orig_patent_app_number] => 09569944 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/569944
Method and apparatus for performing computations using residue arithmetic May 11, 2000 Issued
Array ( [id] => 146221 [patent_doc_number] => 07689637 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-30 [patent_title] => 'Adaptive filtering method and related device' [patent_app_type] => utility [patent_app_number] => 09/564427 [patent_app_country] => US [patent_app_date] => 2000-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 4179 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689637.pdf [firstpage_image] =>[orig_patent_app_number] => 09564427 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/564427
Adaptive filtering method and related device May 3, 2000 Issued
09/562906 Multiplier for the fraction multiplicators May 1, 2000 Abandoned
Array ( [id] => 949897 [patent_doc_number] => 06963895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'Floating point pipeline method and circuit for fast inverse square root calculations' [patent_app_type] => utility [patent_app_number] => 09/562056 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2596 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963895.pdf [firstpage_image] =>[orig_patent_app_number] => 09562056 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562056
Floating point pipeline method and circuit for fast inverse square root calculations Apr 30, 2000 Issued
Array ( [id] => 1250160 [patent_doc_number] => 06675184 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Adaptive type signal estimator' [patent_app_type] => B1 [patent_app_number] => 09/559217 [patent_app_country] => US [patent_app_date] => 2000-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3377 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675184.pdf [firstpage_image] =>[orig_patent_app_number] => 09559217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/559217
Adaptive type signal estimator Apr 25, 2000 Issued
Array ( [id] => 1365630 [patent_doc_number] => 06584485 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => '4 to 2 adder' [patent_app_type] => B1 [patent_app_number] => 09/549766 [patent_app_country] => US [patent_app_date] => 2000-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2321 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584485.pdf [firstpage_image] =>[orig_patent_app_number] => 09549766 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/549766
4 to 2 adder Apr 13, 2000 Issued
Array ( [id] => 1573618 [patent_doc_number] => 06499044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Leading zero/one anticipator for floating point' [patent_app_type] => B1 [patent_app_number] => 09/546412 [patent_app_country] => US [patent_app_date] => 2000-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 9421 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499044.pdf [firstpage_image] =>[orig_patent_app_number] => 09546412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/546412
Leading zero/one anticipator for floating point Apr 9, 2000 Issued
Array ( [id] => 1356215 [patent_doc_number] => 06591282 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Apparatus and method for a DC-Insensitive FIR filter for optical PRML channel' [patent_app_type] => B1 [patent_app_number] => 09/543147 [patent_app_country] => US [patent_app_date] => 2000-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2307 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591282.pdf [firstpage_image] =>[orig_patent_app_number] => 09543147 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/543147
Apparatus and method for a DC-Insensitive FIR filter for optical PRML channel Apr 4, 2000 Issued
Array ( [id] => 1338642 [patent_doc_number] => 06601077 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'DSP unit for multi-level global accumulation' [patent_app_type] => B1 [patent_app_number] => 09/541148 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3463 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601077.pdf [firstpage_image] =>[orig_patent_app_number] => 09541148 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541148
DSP unit for multi-level global accumulation Mar 30, 2000 Issued
09/539922 Multipler architecture in a general purpose processor optimized for efficient multi-input addition Mar 30, 2000 Abandoned
Array ( [id] => 1384821 [patent_doc_number] => 06571264 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Floating-point arithmetic device' [patent_app_type] => B1 [patent_app_number] => 09/541679 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5061 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571264.pdf [firstpage_image] =>[orig_patent_app_number] => 09541679 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541679
Floating-point arithmetic device Mar 30, 2000 Issued
Array ( [id] => 1296718 [patent_doc_number] => 06633896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Method and system for multiplying large numbers' [patent_app_type] => B1 [patent_app_number] => 09/538174 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3917 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633896.pdf [firstpage_image] =>[orig_patent_app_number] => 09538174 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/538174
Method and system for multiplying large numbers Mar 29, 2000 Issued
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