Search

William A Powell

Examiner (ID: 17926)

Most Active Art Unit
1765
Art Unit(s)
1104, 1763, 1106, 1765, 1109, 1301, 1307, 3202, 1502, 1304, 1303
Total Applications
3597
Issued Applications
3357
Pending Applications
97
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4378610 [patent_doc_number] => 06303506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Compositions for and method of reducing/eliminating scratches and defects in silicon dioxide during CMP process' [patent_app_type] => 1 [patent_app_number] => 9/409464 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2335 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303506.pdf [firstpage_image] =>[orig_patent_app_number] => 409464 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409464
Compositions for and method of reducing/eliminating scratches and defects in silicon dioxide during CMP process Sep 29, 1999 Issued
Array ( [id] => 4380342 [patent_doc_number] => 06261851 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Optimization of CMP process by detecting of oxide/nitride interface using IR system' [patent_app_type] => 1 [patent_app_number] => 9/410265 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3269 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261851.pdf [firstpage_image] =>[orig_patent_app_number] => 410265 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410265
Optimization of CMP process by detecting of oxide/nitride interface using IR system Sep 29, 1999 Issued
Array ( [id] => 1462674 [patent_doc_number] => 06350701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Etching system' [patent_app_type] => B1 [patent_app_number] => 09/408135 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9050 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350701.pdf [firstpage_image] =>[orig_patent_app_number] => 09408135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408135
Etching system Sep 28, 1999 Issued
Array ( [id] => 4407800 [patent_doc_number] => 06239037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Autoaligned etching process for realizing word lines and improving the reliability of semiconductor integrated memory devices' [patent_app_type] => 1 [patent_app_number] => 9/408160 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2881 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239037.pdf [firstpage_image] =>[orig_patent_app_number] => 408160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408160
Autoaligned etching process for realizing word lines and improving the reliability of semiconductor integrated memory devices Sep 27, 1999 Issued
Array ( [id] => 4381908 [patent_doc_number] => 06277753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Removal of CMP residue from semiconductors using supercritical carbon dioxide process' [patent_app_type] => 1 [patent_app_number] => 9/407628 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1695 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277753.pdf [firstpage_image] =>[orig_patent_app_number] => 407628 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/407628
Removal of CMP residue from semiconductors using supercritical carbon dioxide process Sep 27, 1999 Issued
90/005505 METHOD AND COMPOSITION FOR POLISHING METAL SURFACES Sep 23, 1999 Issued
Array ( [id] => 4298846 [patent_doc_number] => 06325948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Waferless clean process of a dry etcher' [patent_app_type] => 1 [patent_app_number] => 9/399359 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2897 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/325/06325948.pdf [firstpage_image] =>[orig_patent_app_number] => 399359 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/399359
Waferless clean process of a dry etcher Sep 19, 1999 Issued
Array ( [id] => 4420815 [patent_doc_number] => 06225233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Semiconductor device manufacturing machine and method for manufacturing a semiconductor device by using THE same manufacturing machine' [patent_app_type] => 1 [patent_app_number] => 9/396877 [patent_app_country] => US [patent_app_date] => 1999-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 8767 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225233.pdf [firstpage_image] =>[orig_patent_app_number] => 396877 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/396877
Semiconductor device manufacturing machine and method for manufacturing a semiconductor device by using THE same manufacturing machine Sep 15, 1999 Issued
Array ( [id] => 4415181 [patent_doc_number] => 06224713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method and apparatus for ultrasonic wet etching of silicon' [patent_app_type] => 1 [patent_app_number] => 9/395777 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3541 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/224/06224713.pdf [firstpage_image] =>[orig_patent_app_number] => 395777 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395777
Method and apparatus for ultrasonic wet etching of silicon Sep 13, 1999 Issued
Array ( [id] => 4420735 [patent_doc_number] => 06225225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method to form shallow trench isolation structures for borderless contacts in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/392395 [patent_app_country] => US [patent_app_date] => 1999-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3014 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225225.pdf [firstpage_image] =>[orig_patent_app_number] => 392395 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392395
Method to form shallow trench isolation structures for borderless contacts in an integrated circuit Sep 8, 1999 Issued
Array ( [id] => 4358950 [patent_doc_number] => 06255219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method for fabricating high-performance submicron MOSFET with lateral asymmetric channel' [patent_app_type] => 1 [patent_app_number] => 9/391303 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 1900 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255219.pdf [firstpage_image] =>[orig_patent_app_number] => 391303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391303
Method for fabricating high-performance submicron MOSFET with lateral asymmetric channel Sep 6, 1999 Issued
Array ( [id] => 4302710 [patent_doc_number] => 06251786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method to create a copper dual damascene structure with less dishing and erosion' [patent_app_type] => 1 [patent_app_number] => 9/390783 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251786.pdf [firstpage_image] =>[orig_patent_app_number] => 390783 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390783
Method to create a copper dual damascene structure with less dishing and erosion Sep 6, 1999 Issued
Array ( [id] => 4250893 [patent_doc_number] => 06207583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Photoresist ashing process for organic and inorganic polymer dielectric materials' [patent_app_type] => 1 [patent_app_number] => 9/390143 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 8521 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207583.pdf [firstpage_image] =>[orig_patent_app_number] => 390143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390143
Photoresist ashing process for organic and inorganic polymer dielectric materials Sep 2, 1999 Issued
Array ( [id] => 4371282 [patent_doc_number] => 06303040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method of fabricating thermooptic tunable wavelength filter' [patent_app_type] => 1 [patent_app_number] => 9/389459 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2524 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303040.pdf [firstpage_image] =>[orig_patent_app_number] => 389459 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389459
Method of fabricating thermooptic tunable wavelength filter Sep 2, 1999 Issued
Array ( [id] => 4293064 [patent_doc_number] => 06180535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Approach to the spacer etch process for CMOS image sensor' [patent_app_type] => 1 [patent_app_number] => 9/389886 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3504 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180535.pdf [firstpage_image] =>[orig_patent_app_number] => 389886 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389886
Approach to the spacer etch process for CMOS image sensor Sep 2, 1999 Issued
Array ( [id] => 4369612 [patent_doc_number] => 06287981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Electrode for generating a plasma and a plasma processing apparatus using the same' [patent_app_type] => 1 [patent_app_number] => 9/389027 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4025 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287981.pdf [firstpage_image] =>[orig_patent_app_number] => 389027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389027
Electrode for generating a plasma and a plasma processing apparatus using the same Sep 1, 1999 Issued
Array ( [id] => 4310906 [patent_doc_number] => 06316363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Deadhesion method and mechanism for wafer processing' [patent_app_type] => 1 [patent_app_number] => 9/387429 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 13818 [patent_no_of_claims] => 183 [patent_no_of_ind_claims] => 29 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316363.pdf [firstpage_image] =>[orig_patent_app_number] => 387429 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387429
Deadhesion method and mechanism for wafer processing Sep 1, 1999 Issued
09/389643 METHOD AND APPARATUS FOR CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC SUBSTRATES WITH SELECTED PLANARIZING LIQUIDS Sep 1, 1999 Abandoned
Array ( [id] => 4250869 [patent_doc_number] => 06207581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method of fabricating node contact hole' [patent_app_type] => 1 [patent_app_number] => 9/387094 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1595 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207581.pdf [firstpage_image] =>[orig_patent_app_number] => 387094 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387094
Method of fabricating node contact hole Aug 31, 1999 Issued
Array ( [id] => 4408792 [patent_doc_number] => 06265319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Dual damascene method employing spin-on polymer (SOP) etch stop layer' [patent_app_type] => 1 [patent_app_number] => 9/387440 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 6204 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265319.pdf [firstpage_image] =>[orig_patent_app_number] => 387440 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387440
Dual damascene method employing spin-on polymer (SOP) etch stop layer Aug 31, 1999 Issued
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