
William A Powell
Examiner (ID: 17926)
| Most Active Art Unit | 1765 |
| Art Unit(s) | 1104, 1763, 1106, 1765, 1109, 1301, 1307, 3202, 1502, 1304, 1303 |
| Total Applications | 3597 |
| Issued Applications | 3357 |
| Pending Applications | 97 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4234316
[patent_doc_number] => 06074950
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-13
[patent_title] => 'Alignment strategy for asymmetrical alignment marks'
[patent_app_type] => 1
[patent_app_number] => 9/234976
[patent_app_country] => US
[patent_app_date] => 1999-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1155
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/074/06074950.pdf
[firstpage_image] =>[orig_patent_app_number] => 234976
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/234976 | Alignment strategy for asymmetrical alignment marks | Jan 21, 1999 | Issued |
Array
(
[id] => 4189148
[patent_doc_number] => 06153533
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Method of using a compliant process cassette'
[patent_app_type] => 1
[patent_app_number] => 9/235091
[patent_app_country] => US
[patent_app_date] => 1999-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 28
[patent_no_of_words] => 4839
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[firstpage_image] =>[orig_patent_app_number] => 235091
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/235091 | Method of using a compliant process cassette | Jan 20, 1999 | Issued |
Array
(
[id] => 4238841
[patent_doc_number] => 06080681
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'Method of forming wiring pattern'
[patent_app_type] => 1
[patent_app_number] => 9/234576
[patent_app_country] => US
[patent_app_date] => 1999-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 4169
[patent_no_of_claims] => 39
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[patent_words_short_claim] => 137
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[pdf_file] => patents/06/080/06080681.pdf
[firstpage_image] =>[orig_patent_app_number] => 234576
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/234576 | Method of forming wiring pattern | Jan 20, 1999 | Issued |
Array
(
[id] => 4140073
[patent_doc_number] => 06063299
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Manufacture of a silicon waveguide structure'
[patent_app_type] => 1
[patent_app_number] => 9/229424
[patent_app_country] => US
[patent_app_date] => 1999-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1758
[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/063/06063299.pdf
[firstpage_image] =>[orig_patent_app_number] => 229424
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/229424 | Manufacture of a silicon waveguide structure | Jan 12, 1999 | Issued |
Array
(
[id] => 3994430
[patent_doc_number] => 05985767
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Facet etch for improved step coverage of integrated circuit contacts'
[patent_app_type] => 1
[patent_app_number] => 9/228725
[patent_app_country] => US
[patent_app_date] => 1999-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4635
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[pdf_file] => patents/05/985/05985767.pdf
[firstpage_image] =>[orig_patent_app_number] => 228725
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/228725 | Facet etch for improved step coverage of integrated circuit contacts | Jan 11, 1999 | Issued |
Array
(
[id] => 4117414
[patent_doc_number] => 06071828
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Semiconductor device manufacturing method including plasma etching step'
[patent_app_type] => 1
[patent_app_number] => 9/228565
[patent_app_country] => US
[patent_app_date] => 1999-01-12
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[pdf_file] => patents/06/071/06071828.pdf
[firstpage_image] =>[orig_patent_app_number] => 228565
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/228565 | Semiconductor device manufacturing method including plasma etching step | Jan 11, 1999 | Issued |
Array
(
[id] => 4030233
[patent_doc_number] => 05994237
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Semiconductor processing methods of forming a contact opening to a semiconductor substrate'
[patent_app_type] => 1
[patent_app_number] => 9/227391
[patent_app_country] => US
[patent_app_date] => 1999-01-08
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 2681
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[pdf_file] => patents/05/994/05994237.pdf
[firstpage_image] =>[orig_patent_app_number] => 227391
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/227391 | Semiconductor processing methods of forming a contact opening to a semiconductor substrate | Jan 7, 1999 | Issued |
Array
(
[id] => 4237751
[patent_doc_number] => 06090715
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-18
[patent_title] => 'Masking process for forming self-aligned dual wells or self-aligned field-doping regions'
[patent_app_type] => 1
[patent_app_number] => 9/223458
[patent_app_country] => US
[patent_app_date] => 1998-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 6
[patent_no_of_words] => 1215
[patent_no_of_claims] => 14
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[pdf_file] => patents/06/090/06090715.pdf
[firstpage_image] =>[orig_patent_app_number] => 223458
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/223458 | Masking process for forming self-aligned dual wells or self-aligned field-doping regions | Dec 29, 1998 | Issued |
Array
(
[id] => 1318534
[patent_doc_number] => 06605538
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-12
[patent_title] => 'Methods for forming ferroelectric capacitors'
[patent_app_type] => B2
[patent_app_number] => 09/221621
[patent_app_country] => US
[patent_app_date] => 1998-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 1153
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[pdf_file] => patents/06/605/06605538.pdf
[firstpage_image] =>[orig_patent_app_number] => 09221621
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/221621 | Methods for forming ferroelectric capacitors | Dec 27, 1998 | Issued |
Array
(
[id] => 4155076
[patent_doc_number] => 06103634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-15
[patent_title] => 'Removal of inorganic anti-reflective coating using fluorine etch process'
[patent_app_type] => 1
[patent_app_number] => 9/215071
[patent_app_country] => US
[patent_app_date] => 1998-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => patents/06/103/06103634.pdf
[firstpage_image] =>[orig_patent_app_number] => 215071
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/215071 | Removal of inorganic anti-reflective coating using fluorine etch process | Dec 17, 1998 | Issued |
Array
(
[id] => 4071363
[patent_doc_number] => 06069089
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-30
[patent_title] => 'Defective semiconductor redistribution labeling system'
[patent_app_type] => 1
[patent_app_number] => 9/216887
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[patent_app_date] => 1998-12-18
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[pdf_file] => patents/06/069/06069089.pdf
[firstpage_image] =>[orig_patent_app_number] => 216887
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/216887 | Defective semiconductor redistribution labeling system | Dec 17, 1998 | Issued |
Array
(
[id] => 4309591
[patent_doc_number] => 06316276
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'Apparatus and method of planarizing a semiconductor wafer that includes a first reflective substance and a second reflective substance'
[patent_app_type] => 1
[patent_app_number] => 9/213803
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[firstpage_image] =>[orig_patent_app_number] => 213803
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/213803 | Apparatus and method of planarizing a semiconductor wafer that includes a first reflective substance and a second reflective substance | Dec 16, 1998 | Issued |
Array
(
[id] => 4417636
[patent_doc_number] => 06194323
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[patent_issue_date] => 2001-02-27
[patent_title] => 'Deep sub-micron metal etch with in-situ hard mask etch'
[patent_app_type] => 1
[patent_app_number] => 9/212228
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Array
(
[id] => 4098231
[patent_doc_number] => 06048796
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[patent_title] => 'Method of manufacturing multilevel metal interconnect'
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[patent_app_number] => 9/211891
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[firstpage_image] =>[orig_patent_app_number] => 211891
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/211891 | Method of manufacturing multilevel metal interconnect | Dec 14, 1998 | Issued |
Array
(
[id] => 4125706
[patent_doc_number] => 06127281
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[patent_title] => 'Porous region removing method and semiconductor substrate manufacturing method'
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Array
(
[id] => 7065006
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[patent_title] => 'POROUS REGION REMOVING METHOD AND SEMICONDUCTOR SUBSTRATE MANUFACTURING METHOD'
[patent_app_type] => new
[patent_app_number] => 09/211738
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Array
(
[id] => 4114275
[patent_doc_number] => 06046112
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[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Chemical mechanical polishing slurry'
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[patent_app_number] => 9/211273
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/211273 | Chemical mechanical polishing slurry | Dec 13, 1998 | Issued |
Array
(
[id] => 4155034
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Array
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Array
(
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