Search

William A Powell

Examiner (ID: 17926)

Most Active Art Unit
1765
Art Unit(s)
1104, 1763, 1106, 1765, 1109, 1301, 1307, 3202, 1502, 1304, 1303
Total Applications
3597
Issued Applications
3357
Pending Applications
97
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4071404 [patent_doc_number] => 06069092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Dry etching method and semiconductor device fabrication method' [patent_app_type] => 1 [patent_app_number] => 9/178431 [patent_app_country] => US [patent_app_date] => 1998-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5801 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069092.pdf [firstpage_image] =>[orig_patent_app_number] => 178431 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178431
Dry etching method and semiconductor device fabrication method Oct 25, 1998 Issued
Array ( [id] => 4139823 [patent_doc_number] => 06060401 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method of fabricating dual cylindrical capacitor' [patent_app_type] => 1 [patent_app_number] => 9/178273 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1343 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060401.pdf [firstpage_image] =>[orig_patent_app_number] => 178273 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178273
Method of fabricating dual cylindrical capacitor Oct 22, 1998 Issued
Array ( [id] => 4178483 [patent_doc_number] => 06037271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Low haze wafer treatment process' [patent_app_type] => 1 [patent_app_number] => 9/176588 [patent_app_country] => US [patent_app_date] => 1998-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3257 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037271.pdf [firstpage_image] =>[orig_patent_app_number] => 176588 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176588
Low haze wafer treatment process Oct 20, 1998 Issued
Array ( [id] => 4197906 [patent_doc_number] => 06013579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Self-aligned via process for preventing poison via formation' [patent_app_type] => 1 [patent_app_number] => 9/176385 [patent_app_country] => US [patent_app_date] => 1998-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2070 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/013/06013579.pdf [firstpage_image] =>[orig_patent_app_number] => 176385 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176385
Self-aligned via process for preventing poison via formation Oct 20, 1998 Issued
Array ( [id] => 3896804 [patent_doc_number] => 05897378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Method of monitoring deposit in chamber, method of plasma processing, method of dry-cleaning chamber, and semiconductor manufacturing apparatus' [patent_app_type] => 1 [patent_app_number] => 9/174555 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 10725 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897378.pdf [firstpage_image] =>[orig_patent_app_number] => 174555 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/174555
Method of monitoring deposit in chamber, method of plasma processing, method of dry-cleaning chamber, and semiconductor manufacturing apparatus Oct 18, 1998 Issued
Array ( [id] => 4246897 [patent_doc_number] => 06136722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Plasma etching method for forming hole in masked silicon dioxide' [patent_app_type] => 1 [patent_app_number] => 9/172860 [patent_app_country] => US [patent_app_date] => 1998-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136722.pdf [firstpage_image] =>[orig_patent_app_number] => 172860 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172860
Plasma etching method for forming hole in masked silicon dioxide Oct 14, 1998 Issued
Array ( [id] => 4102963 [patent_doc_number] => 06051507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method of fabricating capacitor with high capacitance' [patent_app_type] => 1 [patent_app_number] => 9/172406 [patent_app_country] => US [patent_app_date] => 1998-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1906 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051507.pdf [firstpage_image] =>[orig_patent_app_number] => 172406 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172406
Method of fabricating capacitor with high capacitance Oct 13, 1998 Issued
Array ( [id] => 4205441 [patent_doc_number] => 06077789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method for forming a passivation layer with planarization' [patent_app_type] => 1 [patent_app_number] => 9/172535 [patent_app_country] => US [patent_app_date] => 1998-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2244 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077789.pdf [firstpage_image] =>[orig_patent_app_number] => 172535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172535
Method for forming a passivation layer with planarization Oct 13, 1998 Issued
Array ( [id] => 4207208 [patent_doc_number] => 06028011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Method of forming electric pad of semiconductor device and method of forming solder bump' [patent_app_type] => 1 [patent_app_number] => 9/170633 [patent_app_country] => US [patent_app_date] => 1998-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 30 [patent_no_of_words] => 7304 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028011.pdf [firstpage_image] =>[orig_patent_app_number] => 170633 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/170633
Method of forming electric pad of semiconductor device and method of forming solder bump Oct 12, 1998 Issued
Array ( [id] => 4181785 [patent_doc_number] => 06020272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Method for forming suspended micromechanical structures' [patent_app_type] => 1 [patent_app_number] => 9/169307 [patent_app_country] => US [patent_app_date] => 1998-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 53 [patent_no_of_words] => 11387 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020272.pdf [firstpage_image] =>[orig_patent_app_number] => 169307 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169307
Method for forming suspended micromechanical structures Oct 7, 1998 Issued
Array ( [id] => 4169938 [patent_doc_number] => 06140244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method for forming a spacer' [patent_app_type] => 1 [patent_app_number] => 9/167100 [patent_app_country] => US [patent_app_date] => 1998-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2625 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140244.pdf [firstpage_image] =>[orig_patent_app_number] => 167100 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/167100
Method for forming a spacer Oct 4, 1998 Issued
Array ( [id] => 4086020 [patent_doc_number] => 06017826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Chlorine containing plasma etch method with enhanced sidewall passivation and attenuated microloading effect' [patent_app_type] => 1 [patent_app_number] => 9/166746 [patent_app_country] => US [patent_app_date] => 1998-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7962 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/017/06017826.pdf [firstpage_image] =>[orig_patent_app_number] => 166746 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/166746
Chlorine containing plasma etch method with enhanced sidewall passivation and attenuated microloading effect Oct 4, 1998 Issued
Array ( [id] => 4197933 [patent_doc_number] => 06013581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Method for preventing poisoned vias and trenches' [patent_app_type] => 1 [patent_app_number] => 9/166821 [patent_app_country] => US [patent_app_date] => 1998-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1823 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/013/06013581.pdf [firstpage_image] =>[orig_patent_app_number] => 166821 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/166821
Method for preventing poisoned vias and trenches Oct 4, 1998 Issued
Array ( [id] => 4072611 [patent_doc_number] => RE036810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Plasma processing apparatus and method' [patent_app_type] => 2 [patent_app_number] => 9/165545 [patent_app_country] => US [patent_app_date] => 1998-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6420 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036810.pdf [firstpage_image] =>[orig_patent_app_number] => 165545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/165545
Plasma processing apparatus and method Oct 1, 1998 Issued
Array ( [id] => 4136808 [patent_doc_number] => 06015755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Method of fabricating a trench isolation structure using a reverse mask' [patent_app_type] => 1 [patent_app_number] => 9/162576 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/015/06015755.pdf [firstpage_image] =>[orig_patent_app_number] => 162576 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162576
Method of fabricating a trench isolation structure using a reverse mask Sep 28, 1998 Issued
Array ( [id] => 4178415 [patent_doc_number] => 06037266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Method for patterning a polysilicon gate with a thin gate oxide in a polysilicon etcher' [patent_app_type] => 1 [patent_app_number] => 9/161567 [patent_app_country] => US [patent_app_date] => 1998-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3935 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037266.pdf [firstpage_image] =>[orig_patent_app_number] => 161567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/161567
Method for patterning a polysilicon gate with a thin gate oxide in a polysilicon etcher Sep 27, 1998 Issued
Array ( [id] => 3911580 [patent_doc_number] => 06001743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Method for fabricating a self-aligned contact' [patent_app_type] => 1 [patent_app_number] => 9/149736 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1472 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001743.pdf [firstpage_image] =>[orig_patent_app_number] => 149736 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/149736
Method for fabricating a self-aligned contact Sep 7, 1998 Issued
Array ( [id] => 4085301 [patent_doc_number] => 06025276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Semiconductor processing methods of forming substrate features, including contact openings' [patent_app_type] => 1 [patent_app_number] => 9/146844 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2820 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025276.pdf [firstpage_image] =>[orig_patent_app_number] => 146844 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146844
Semiconductor processing methods of forming substrate features, including contact openings Sep 2, 1998 Issued
Array ( [id] => 4186301 [patent_doc_number] => 06093652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Methods of forming insulative plugs, and oxide plug forming methods' [patent_app_type] => 1 [patent_app_number] => 9/146765 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2478 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093652.pdf [firstpage_image] =>[orig_patent_app_number] => 146765 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146765
Methods of forming insulative plugs, and oxide plug forming methods Sep 2, 1998 Issued
Array ( [id] => 4114262 [patent_doc_number] => 06046111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Method and apparatus for endpointing mechanical and chemical-mechanical planarization of microelectronic substrates' [patent_app_type] => 1 [patent_app_number] => 9/146330 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4707 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046111.pdf [firstpage_image] =>[orig_patent_app_number] => 146330 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146330
Method and apparatus for endpointing mechanical and chemical-mechanical planarization of microelectronic substrates Sep 1, 1998 Issued
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