
William A Powell
Examiner (ID: 17926)
| Most Active Art Unit | 1765 |
| Art Unit(s) | 1104, 1763, 1106, 1765, 1109, 1301, 1307, 3202, 1502, 1304, 1303 |
| Total Applications | 3597 |
| Issued Applications | 3357 |
| Pending Applications | 97 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3911522
[patent_doc_number] => 06001739
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Method of manufacturing a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/979658
[patent_app_country] => US
[patent_app_date] => 1997-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 27
[patent_no_of_words] => 4945
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/001/06001739.pdf
[firstpage_image] =>[orig_patent_app_number] => 979658
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/979658 | Method of manufacturing a semiconductor device | Nov 25, 1997 | Issued |
Array
(
[id] => 4024440
[patent_doc_number] => 05883008
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-16
[patent_title] => 'Integrated circuit die suitable for wafer-level testing and method for forming the same'
[patent_app_type] => 1
[patent_app_number] => 8/979019
[patent_app_country] => US
[patent_app_date] => 1997-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 14558
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/883/05883008.pdf
[firstpage_image] =>[orig_patent_app_number] => 979019
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/979019 | Integrated circuit die suitable for wafer-level testing and method for forming the same | Nov 25, 1997 | Issued |
Array
(
[id] => 3955716
[patent_doc_number] => 05900072
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Insulating layer structure for semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/978595
[patent_app_country] => US
[patent_app_date] => 1997-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 2078
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/900/05900072.pdf
[firstpage_image] =>[orig_patent_app_number] => 978595
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/978595 | Insulating layer structure for semiconductor device | Nov 24, 1997 | Issued |
Array
(
[id] => 4146289
[patent_doc_number] => 06063712
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Oxide etch and method of etching'
[patent_app_type] => 1
[patent_app_number] => 8/977783
[patent_app_country] => US
[patent_app_date] => 1997-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 3439
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 15
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/063/06063712.pdf
[firstpage_image] =>[orig_patent_app_number] => 977783
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/977783 | Oxide etch and method of etching | Nov 24, 1997 | Issued |
Array
(
[id] => 3868011
[patent_doc_number] => 05837613
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Enhanced planarization technique for an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/976760
[patent_app_country] => US
[patent_app_date] => 1997-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 2574
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/837/05837613.pdf
[firstpage_image] =>[orig_patent_app_number] => 976760
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/976760 | Enhanced planarization technique for an integrated circuit | Nov 23, 1997 | Issued |
Array
(
[id] => 4080130
[patent_doc_number] => 06017463
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Point of use mixing for LI/plug tungsten polishing slurry to improve existing slurry'
[patent_app_type] => 1
[patent_app_number] => 8/976026
[patent_app_country] => US
[patent_app_date] => 1997-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3883
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/017/06017463.pdf
[firstpage_image] =>[orig_patent_app_number] => 976026
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/976026 | Point of use mixing for LI/plug tungsten polishing slurry to improve existing slurry | Nov 20, 1997 | Issued |
Array
(
[id] => 4054145
[patent_doc_number] => 05865891
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'Planarization process using artificial gravity'
[patent_app_type] => 1
[patent_app_number] => 8/974460
[patent_app_country] => US
[patent_app_date] => 1997-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2441
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/865/05865891.pdf
[firstpage_image] =>[orig_patent_app_number] => 974460
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/974460 | Planarization process using artificial gravity | Nov 19, 1997 | Issued |
Array
(
[id] => 4130556
[patent_doc_number] => 06033989
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Device for and method of concentrating chemical substances for semiconductor fabrication'
[patent_app_type] => 1
[patent_app_number] => 8/974319
[patent_app_country] => US
[patent_app_date] => 1997-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4645
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/033/06033989.pdf
[firstpage_image] =>[orig_patent_app_number] => 974319
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/974319 | Device for and method of concentrating chemical substances for semiconductor fabrication | Nov 18, 1997 | Issued |
Array
(
[id] => 4185072
[patent_doc_number] => 06042736
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Method for preparing samples for microscopic examination'
[patent_app_type] => 1
[patent_app_number] => 8/971893
[patent_app_country] => US
[patent_app_date] => 1997-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 13
[patent_no_of_words] => 3822
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/042/06042736.pdf
[firstpage_image] =>[orig_patent_app_number] => 971893
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/971893 | Method for preparing samples for microscopic examination | Nov 16, 1997 | Issued |
Array
(
[id] => 4108112
[patent_doc_number] => 06045713
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Method of manufacturing a 2-layered flexible substrate'
[patent_app_type] => 1
[patent_app_number] => 8/970210
[patent_app_country] => US
[patent_app_date] => 1997-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9551
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/045/06045713.pdf
[firstpage_image] =>[orig_patent_app_number] => 970210
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/970210 | Method of manufacturing a 2-layered flexible substrate | Nov 13, 1997 | Issued |
Array
(
[id] => 3794892
[patent_doc_number] => 05841196
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Fluted via formation for superior metal step coverage'
[patent_app_type] => 1
[patent_app_number] => 8/970314
[patent_app_country] => US
[patent_app_date] => 1997-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4044
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/841/05841196.pdf
[firstpage_image] =>[orig_patent_app_number] => 970314
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/970314 | Fluted via formation for superior metal step coverage | Nov 13, 1997 | Issued |
Array
(
[id] => 3978668
[patent_doc_number] => 05948702
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'Selective removal of TixNy'
[patent_app_type] => 1
[patent_app_number] => 8/966935
[patent_app_country] => US
[patent_app_date] => 1997-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 9
[patent_no_of_words] => 3119
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/948/05948702.pdf
[firstpage_image] =>[orig_patent_app_number] => 966935
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/966935 | Selective removal of TixNy | Nov 9, 1997 | Issued |
Array
(
[id] => 3956624
[patent_doc_number] => 05982630
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Printed circuit board that provides improved thermal dissipation'
[patent_app_type] => 1
[patent_app_number] => 8/965354
[patent_app_country] => US
[patent_app_date] => 1997-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3015
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/982/05982630.pdf
[firstpage_image] =>[orig_patent_app_number] => 965354
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/965354 | Printed circuit board that provides improved thermal dissipation | Nov 5, 1997 | Issued |
Array
(
[id] => 4095349
[patent_doc_number] => 06096652
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Method of chemical mechanical planarization using copper coordinating ligands'
[patent_app_type] => 1
[patent_app_number] => 8/963438
[patent_app_country] => US
[patent_app_date] => 1997-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3748
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/096/06096652.pdf
[firstpage_image] =>[orig_patent_app_number] => 963438
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/963438 | Method of chemical mechanical planarization using copper coordinating ligands | Nov 2, 1997 | Issued |
Array
(
[id] => 3926922
[patent_doc_number] => 05972231
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'Imbedded PCB AC coupling capacitors for high data rate signal transfer'
[patent_app_type] => 1
[patent_app_number] => 8/962065
[patent_app_country] => US
[patent_app_date] => 1997-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 3723
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/972/05972231.pdf
[firstpage_image] =>[orig_patent_app_number] => 962065
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/962065 | Imbedded PCB AC coupling capacitors for high data rate signal transfer | Oct 30, 1997 | Issued |
Array
(
[id] => 4015672
[patent_doc_number] => 05906753
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-25
[patent_title] => 'Method of making optical semi-conductor device'
[patent_app_type] => 1
[patent_app_number] => 8/961145
[patent_app_country] => US
[patent_app_date] => 1997-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 53
[patent_no_of_words] => 7540
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/906/05906753.pdf
[firstpage_image] =>[orig_patent_app_number] => 961145
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/961145 | Method of making optical semi-conductor device | Oct 29, 1997 | Issued |
Array
(
[id] => 4058190
[patent_doc_number] => 06007728
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'Design of a novel tactile sensor'
[patent_app_type] => 1
[patent_app_number] => 8/961126
[patent_app_country] => US
[patent_app_date] => 1997-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4304
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/007/06007728.pdf
[firstpage_image] =>[orig_patent_app_number] => 961126
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/961126 | Design of a novel tactile sensor | Oct 29, 1997 | Issued |
Array
(
[id] => 3982931
[patent_doc_number] => 05861344
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-19
[patent_title] => 'Facet etch for improved step coverage of integrated circuit contacts'
[patent_app_type] => 1
[patent_app_number] => 8/958655
[patent_app_country] => US
[patent_app_date] => 1997-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 4637
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/861/05861344.pdf
[firstpage_image] =>[orig_patent_app_number] => 958655
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/958655 | Facet etch for improved step coverage of integrated circuit contacts | Oct 26, 1997 | Issued |
Array
(
[id] => 4073016
[patent_doc_number] => 05965462
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-12
[patent_title] => 'Method for forming a gate structure used in borderless contact etching'
[patent_app_type] => 1
[patent_app_number] => 8/958385
[patent_app_country] => US
[patent_app_date] => 1997-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 2482
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 29
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/965/05965462.pdf
[firstpage_image] =>[orig_patent_app_number] => 958385
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/958385 | Method for forming a gate structure used in borderless contact etching | Oct 26, 1997 | Issued |
Array
(
[id] => 3733753
[patent_doc_number] => 05785797
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-28
[patent_title] => 'Method and apparatus for monitoring etching by products'
[patent_app_type] => 1
[patent_app_number] => 8/954920
[patent_app_country] => US
[patent_app_date] => 1997-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1834
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/785/05785797.pdf
[firstpage_image] =>[orig_patent_app_number] => 954920
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/954920 | Method and apparatus for monitoring etching by products | Oct 20, 1997 | Issued |