Search

William A. Powell

Examiner (ID: 12339)

Most Active Art Unit
1765
Art Unit(s)
1307, 1109, 1301, 1304, 1303, 1765, 1106, 1104, 1763, 1502, 3202
Total Applications
3597
Issued Applications
3357
Pending Applications
97
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3987829 [patent_doc_number] => 05919378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Process for automatically making printing sleeves' [patent_app_type] => 1 [patent_app_number] => 8/884727 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1756 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/919/05919378.pdf [firstpage_image] =>[orig_patent_app_number] => 884727 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884727
Process for automatically making printing sleeves Jun 29, 1997 Issued
Array ( [id] => 3923167 [patent_doc_number] => 05914276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Methods of forming electrically conductive lines using nitrogen and chlorine containing gas mixtures' [patent_app_type] => 1 [patent_app_number] => 8/885336 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2562 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/914/05914276.pdf [firstpage_image] =>[orig_patent_app_number] => 885336 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885336
Methods of forming electrically conductive lines using nitrogen and chlorine containing gas mixtures Jun 29, 1997 Issued
Array ( [id] => 4044516 [patent_doc_number] => 05912184 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Environmentally enhanced enclosure for managing CMP contamination' [patent_app_type] => 1 [patent_app_number] => 8/884585 [patent_app_country] => US [patent_app_date] => 1997-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3506 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912184.pdf [firstpage_image] =>[orig_patent_app_number] => 884585 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884585
Environmentally enhanced enclosure for managing CMP contamination Jun 27, 1997 Issued
Array ( [id] => 4057608 [patent_doc_number] => 05895273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Silicon sidewall etching' [patent_app_type] => 1 [patent_app_number] => 8/883762 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895273.pdf [firstpage_image] =>[orig_patent_app_number] => 883762 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883762
Silicon sidewall etching Jun 26, 1997 Issued
Array ( [id] => 4102950 [patent_doc_number] => 06051506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method of fabrication ultra-frequency semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/883201 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 1604 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051506.pdf [firstpage_image] =>[orig_patent_app_number] => 883201 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883201
Method of fabrication ultra-frequency semiconductor device Jun 25, 1997 Issued
Array ( [id] => 4172642 [patent_doc_number] => 06036876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Dry-etching of indium and tin oxides' [patent_app_type] => 1 [patent_app_number] => 8/881950 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3583 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/036/06036876.pdf [firstpage_image] =>[orig_patent_app_number] => 881950 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881950
Dry-etching of indium and tin oxides Jun 24, 1997 Issued
Array ( [id] => 3849684 [patent_doc_number] => 05767021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Dry etching method, chemical vapor deposition method, and apparatus for processing semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 8/882108 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 43 [patent_no_of_words] => 15233 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767021.pdf [firstpage_image] =>[orig_patent_app_number] => 882108 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882108
Dry etching method, chemical vapor deposition method, and apparatus for processing semiconductor substrate Jun 24, 1997 Issued
Array ( [id] => 4062290 [patent_doc_number] => 05895581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Laser imaging of printed circuit patterns without using phototools' [patent_app_type] => 1 [patent_app_number] => 8/881387 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3669 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895581.pdf [firstpage_image] =>[orig_patent_app_number] => 881387 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881387
Laser imaging of printed circuit patterns without using phototools Jun 23, 1997 Issued
Array ( [id] => 3806951 [patent_doc_number] => 05788855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Method of producing circuit board' [patent_app_type] => 1 [patent_app_number] => 8/880577 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2110 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/788/05788855.pdf [firstpage_image] =>[orig_patent_app_number] => 880577 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/880577
Method of producing circuit board Jun 22, 1997 Issued
Array ( [id] => 3836935 [patent_doc_number] => 05846884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing' [patent_app_type] => 1 [patent_app_number] => 8/879727 [patent_app_country] => US [patent_app_date] => 1997-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4966 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/846/05846884.pdf [firstpage_image] =>[orig_patent_app_number] => 879727 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879727
Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing Jun 19, 1997 Issued
Array ( [id] => 4024480 [patent_doc_number] => 05883011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Method of removing an inorganic antireflective coating from a semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 8/878451 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3268 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883011.pdf [firstpage_image] =>[orig_patent_app_number] => 878451 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878451
Method of removing an inorganic antireflective coating from a semiconductor substrate Jun 17, 1997 Issued
Array ( [id] => 3926514 [patent_doc_number] => 05877092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Method for edge profile and design rules control' [patent_app_type] => 1 [patent_app_number] => 8/877985 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2557 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877092.pdf [firstpage_image] =>[orig_patent_app_number] => 877985 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877985
Method for edge profile and design rules control Jun 17, 1997 Issued
Array ( [id] => 4038762 [patent_doc_number] => 05968279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Method of cleaning wafer substrates' [patent_app_type] => 1 [patent_app_number] => 8/874851 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2455 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968279.pdf [firstpage_image] =>[orig_patent_app_number] => 874851 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874851
Method of cleaning wafer substrates Jun 12, 1997 Issued
Array ( [id] => 4044562 [patent_doc_number] => 05912187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Method of fabricating circuits' [patent_app_type] => 1 [patent_app_number] => 8/871489 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1509 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912187.pdf [firstpage_image] =>[orig_patent_app_number] => 871489 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871489
Method of fabricating circuits Jun 9, 1997 Issued
Array ( [id] => 3896242 [patent_doc_number] => 05897338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Method for encapsulating an integrated semi-conductor circuit' [patent_app_type] => 1 [patent_app_number] => 8/871960 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1777 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897338.pdf [firstpage_image] =>[orig_patent_app_number] => 871960 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871960
Method for encapsulating an integrated semi-conductor circuit Jun 9, 1997 Issued
Array ( [id] => 3954910 [patent_doc_number] => 05935876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Via structure using a composite dielectric layer' [patent_app_type] => 1 [patent_app_number] => 8/872655 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1543 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935876.pdf [firstpage_image] =>[orig_patent_app_number] => 872655 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/872655
Via structure using a composite dielectric layer Jun 9, 1997 Issued
Array ( [id] => 3923823 [patent_doc_number] => 05945355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Integrated circuit fabrication' [patent_app_type] => 1 [patent_app_number] => 8/871383 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1431 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945355.pdf [firstpage_image] =>[orig_patent_app_number] => 871383 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871383
Integrated circuit fabrication Jun 8, 1997 Issued
Array ( [id] => 3820146 [patent_doc_number] => 05783097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Process to avoid dielectric damage at the flat edge of the water' [patent_app_type] => 1 [patent_app_number] => 8/871503 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/783/05783097.pdf [firstpage_image] =>[orig_patent_app_number] => 871503 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871503
Process to avoid dielectric damage at the flat edge of the water Jun 8, 1997 Issued
Array ( [id] => 4005935 [patent_doc_number] => 05879568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Process for producing multilayer printed circuit board for wire bonding' [patent_app_type] => 1 [patent_app_number] => 8/870379 [patent_app_country] => US [patent_app_date] => 1997-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 6297 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/879/05879568.pdf [firstpage_image] =>[orig_patent_app_number] => 870379 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/870379
Process for producing multilayer printed circuit board for wire bonding Jun 5, 1997 Issued
Array ( [id] => 3991462 [patent_doc_number] => 05891808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method for fabricating a die seal' [patent_app_type] => 1 [patent_app_number] => 8/870960 [patent_app_country] => US [patent_app_date] => 1997-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2240 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/891/05891808.pdf [firstpage_image] =>[orig_patent_app_number] => 870960 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/870960
Method for fabricating a die seal Jun 5, 1997 Issued
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