Search

William A. Powell

Examiner (ID: 14143)

Most Active Art Unit
1765
Art Unit(s)
1763, 1304, 1765, 1104, 1303, 3202, 1106, 1502, 1301, 1109, 1307
Total Applications
3597
Issued Applications
3357
Pending Applications
97
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5999495 [patent_doc_number] => 20020028322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Mask for the selective growth of a solid, a manufacturing method for the mask, and a method for selectively growing a solid using the mask' [patent_app_type] => new [patent_app_number] => 09/917711 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4675 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20020028322.pdf [firstpage_image] =>[orig_patent_app_number] => 09917711 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917711
Mask for the selective growth of a solid, a manufacturing method for the mask, and a method for selectively growing a solid using the mask Jul 30, 2001 Issued
Array ( [id] => 1368920 [patent_doc_number] => 06558560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method for the fabrication of electrical contacts' [patent_app_type] => B2 [patent_app_number] => 09/917357 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3286 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/558/06558560.pdf [firstpage_image] =>[orig_patent_app_number] => 09917357 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917357
Method for the fabrication of electrical contacts Jul 26, 2001 Issued
Array ( [id] => 6141877 [patent_doc_number] => 20020001960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Material removal method for forming a structure' [patent_app_type] => new [patent_app_number] => 09/907296 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 49283 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 26 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001960.pdf [firstpage_image] =>[orig_patent_app_number] => 09907296 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/907296
Material removal method for forming a structure Jul 15, 2001 Issued
Array ( [id] => 1288912 [patent_doc_number] => 06632744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-14 [patent_title] => 'Manufacturing method of semiconductor integrated circuit device' [patent_app_type] => B2 [patent_app_number] => 09/903580 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 75 [patent_no_of_words] => 19811 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/632/06632744.pdf [firstpage_image] =>[orig_patent_app_number] => 09903580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/903580
Manufacturing method of semiconductor integrated circuit device Jul 12, 2001 Issued
Array ( [id] => 1337616 [patent_doc_number] => 06585908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-01 [patent_title] => 'Shallow angle interference process and apparatus for determining real-time etching rate' [patent_app_type] => B2 [patent_app_number] => 09/905032 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6035 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/585/06585908.pdf [firstpage_image] =>[orig_patent_app_number] => 09905032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905032
Shallow angle interference process and apparatus for determining real-time etching rate Jul 12, 2001 Issued
Array ( [id] => 1343730 [patent_doc_number] => 06579464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-17 [patent_title] => 'Fixtures for processing a workpiece in a supercritical fluid' [patent_app_type] => B2 [patent_app_number] => 09/903880 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1862 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/579/06579464.pdf [firstpage_image] =>[orig_patent_app_number] => 09903880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/903880
Fixtures for processing a workpiece in a supercritical fluid Jul 11, 2001 Issued
Array ( [id] => 6651452 [patent_doc_number] => 20030008511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide ETCH stop layers' [patent_app_type] => new [patent_app_number] => 09/899420 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6811 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20030008511.pdf [firstpage_image] =>[orig_patent_app_number] => 09899420 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/899420
Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide etch stop layers Jul 4, 2001 Issued
Array ( [id] => 6651460 [patent_doc_number] => 20030008515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Method of fabricating a vertical MOS transistor' [patent_app_type] => new [patent_app_number] => 09/681988 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2737 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20030008515.pdf [firstpage_image] =>[orig_patent_app_number] => 09681988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681988
Method of fabricating a vertical MOS transistor Jul 2, 2001 Abandoned
Array ( [id] => 1346789 [patent_doc_number] => 06583067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Method of avoiding dielectric layer deterioration with a low dielectric constant' [patent_app_type] => B2 [patent_app_number] => 09/681987 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2259 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583067.pdf [firstpage_image] =>[orig_patent_app_number] => 09681987 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681987
Method of avoiding dielectric layer deterioration with a low dielectric constant Jul 2, 2001 Issued
Array ( [id] => 1362106 [patent_doc_number] => 06569770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-27 [patent_title] => 'Method for improving oxide erosion of tungsten CMP operations' [patent_app_type] => B2 [patent_app_number] => 09/893080 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1875 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/569/06569770.pdf [firstpage_image] =>[orig_patent_app_number] => 09893080 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/893080
Method for improving oxide erosion of tungsten CMP operations Jun 27, 2001 Issued
Array ( [id] => 1598450 [patent_doc_number] => 06475399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'Method for fabricating a stencil mask' [patent_app_type] => B2 [patent_app_number] => 09/892552 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2210 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 489 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475399.pdf [firstpage_image] =>[orig_patent_app_number] => 09892552 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/892552
Method for fabricating a stencil mask Jun 27, 2001 Issued
Array ( [id] => 1390893 [patent_doc_number] => 06544898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method for improved die release of a semiconductor device from a wafer' [patent_app_type] => B2 [patent_app_number] => 09/891105 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2136 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544898.pdf [firstpage_image] =>[orig_patent_app_number] => 09891105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/891105
Method for improved die release of a semiconductor device from a wafer Jun 24, 2001 Issued
Array ( [id] => 5996783 [patent_doc_number] => 20020027124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Bio-mediated assembly of micrometer-scale and nanometer-scale structures' [patent_app_type] => new [patent_app_number] => 09/878487 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7558 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20020027124.pdf [firstpage_image] =>[orig_patent_app_number] => 09878487 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878487
Bio-mediated assembly of micrometer-scale and nanometer-scale structures Jun 10, 2001 Abandoned
Array ( [id] => 1570144 [patent_doc_number] => 06498045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Optical intensity modifier' [patent_app_type] => B1 [patent_app_number] => 09/878741 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3461 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498045.pdf [firstpage_image] =>[orig_patent_app_number] => 09878741 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878741
Optical intensity modifier Jun 10, 2001 Issued
Array ( [id] => 1467074 [patent_doc_number] => 06458705 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method for forming via-first dual damascene interconnect structure' [patent_app_type] => B1 [patent_app_number] => 09/874522 [patent_app_country] => US [patent_app_date] => 2001-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458705.pdf [firstpage_image] =>[orig_patent_app_number] => 09874522 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/874522
Method for forming via-first dual damascene interconnect structure Jun 5, 2001 Issued
Array ( [id] => 1517394 [patent_doc_number] => 06500767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method of etching semiconductor metallic layer' [patent_app_type] => B2 [patent_app_number] => 09/874164 [patent_app_country] => US [patent_app_date] => 2001-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1606 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500767.pdf [firstpage_image] =>[orig_patent_app_number] => 09874164 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/874164
Method of etching semiconductor metallic layer Jun 4, 2001 Issued
Array ( [id] => 1323802 [patent_doc_number] => 06599435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Method for controlling flatness of wafer and manufacturing method of thin-film magnetic head' [patent_app_type] => B2 [patent_app_number] => 09/867425 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2143 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/599/06599435.pdf [firstpage_image] =>[orig_patent_app_number] => 09867425 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/867425
Method for controlling flatness of wafer and manufacturing method of thin-film magnetic head May 30, 2001 Issued
Array ( [id] => 1399620 [patent_doc_number] => 06537921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Vertical metal oxide silicon field effect semiconductor diodes' [patent_app_type] => B2 [patent_app_number] => 09/864436 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 37 [patent_no_of_words] => 5304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537921.pdf [firstpage_image] =>[orig_patent_app_number] => 09864436 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864436
Vertical metal oxide silicon field effect semiconductor diodes May 22, 2001 Issued
Array ( [id] => 1359199 [patent_doc_number] => 06573190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Dry etching device and dry etching method' [patent_app_type] => B1 [patent_app_number] => 09/856264 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5123 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573190.pdf [firstpage_image] =>[orig_patent_app_number] => 09856264 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/856264
Dry etching device and dry etching method May 17, 2001 Issued
Array ( [id] => 6121853 [patent_doc_number] => 20020074081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Microelectronic packaging methods and components' [patent_app_type] => new [patent_app_number] => 09/858770 [patent_app_country] => US [patent_app_date] => 2001-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7440 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20020074081.pdf [firstpage_image] =>[orig_patent_app_number] => 09858770 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/858770
Microelectronic packaging methods and components May 15, 2001 Issued
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