Search

William B. Chou

Examiner (ID: 15166, Phone: (571)270-3367 , Office: P/3779 )

Most Active Art Unit
3795
Art Unit(s)
3779, 3795
Total Applications
590
Issued Applications
403
Pending Applications
53
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7321098 [patent_doc_number] => 20040225780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'INFORMATION PROCESSING EQUIPMENT, SIGNAL TRANSFORMATION EQUIPMENT, METHOD OF COMMUNICATIONS, AND COMPUTER PRODUCT' [patent_app_type] => new [patent_app_number] => 09/845331 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12330 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20040225780.pdf [firstpage_image] =>[orig_patent_app_number] => 09845331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845331
Information processing equipment, signal transformation equipment, method of communications, and computer product Apr 30, 2001 Issued
Array ( [id] => 7622385 [patent_doc_number] => 06687781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Fair weighted queuing bandwidth allocation system for network switch port' [patent_app_type] => B2 [patent_app_number] => 09/847078 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9221 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687781.pdf [firstpage_image] =>[orig_patent_app_number] => 09847078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847078
Fair weighted queuing bandwidth allocation system for network switch port Apr 30, 2001 Issued
Array ( [id] => 5791438 [patent_doc_number] => 20020161955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Atomic ownership change operation for input/output (I/O) bridge device in clustered computer system' [patent_app_type] => new [patent_app_number] => 09/844584 [patent_app_country] => US [patent_app_date] => 2001-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5299 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20020161955.pdf [firstpage_image] =>[orig_patent_app_number] => 09844584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/844584
Atomic ownership change operation for input/output (I/O) bridge device in clustered computer system Apr 26, 2001 Issued
Array ( [id] => 5910499 [patent_doc_number] => 20020144036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Multistage configuration and power setting' [patent_app_type] => new [patent_app_number] => 09/823703 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7270 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144036.pdf [firstpage_image] =>[orig_patent_app_number] => 09823703 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823703
Multistage configuration and power setting Mar 29, 2001 Issued
Array ( [id] => 1218106 [patent_doc_number] => 06711640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Split delay transmission line' [patent_app_type] => B1 [patent_app_number] => 09/823147 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1846 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711640.pdf [firstpage_image] =>[orig_patent_app_number] => 09823147 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823147
Split delay transmission line Mar 28, 2001 Issued
Array ( [id] => 7321095 [patent_doc_number] => 20040225778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'SYSTEMS FOR INTERCHIP COMMUNICATION' [patent_app_type] => new [patent_app_number] => 09/817659 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2913 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20040225778.pdf [firstpage_image] =>[orig_patent_app_number] => 09817659 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817659
Systems for interchip communication Mar 25, 2001 Issued
Array ( [id] => 1088534 [patent_doc_number] => 06832278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'PCI bar target operation region' [patent_app_type] => B2 [patent_app_number] => 09/809639 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/832/06832278.pdf [firstpage_image] =>[orig_patent_app_number] => 09809639 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809639
PCI bar target operation region Mar 14, 2001 Issued
Array ( [id] => 1177423 [patent_doc_number] => 06760801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Ground referenced voltage source input/output scheme for multi-drop bus' [patent_app_type] => B1 [patent_app_number] => 09/801028 [patent_app_country] => US [patent_app_date] => 2001-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2018 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760801.pdf [firstpage_image] =>[orig_patent_app_number] => 09801028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/801028
Ground referenced voltage source input/output scheme for multi-drop bus Mar 5, 2001 Issued
Array ( [id] => 1129556 [patent_doc_number] => 06795887 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-21 [patent_title] => 'Modular MFP/printer architectures' [patent_app_type] => B1 [patent_app_number] => 09/800012 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5177 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795887.pdf [firstpage_image] =>[orig_patent_app_number] => 09800012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/800012
Modular MFP/printer architectures Mar 4, 2001 Issued
Array ( [id] => 1183449 [patent_doc_number] => 06751693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Methods for assigning addresses to expanded devices in I/O subsystem' [patent_app_type] => B1 [patent_app_number] => 09/798278 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5388 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751693.pdf [firstpage_image] =>[orig_patent_app_number] => 09798278 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798278
Methods for assigning addresses to expanded devices in I/O subsystem Mar 1, 2001 Issued
Array ( [id] => 1100365 [patent_doc_number] => 06823420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Entertainment apparatus' [patent_app_type] => B2 [patent_app_number] => 09/798695 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1860 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/823/06823420.pdf [firstpage_image] =>[orig_patent_app_number] => 09798695 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798695
Entertainment apparatus Mar 1, 2001 Issued
Array ( [id] => 1196916 [patent_doc_number] => 06732219 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Dynamic allocation of devices to host controllers' [patent_app_type] => B1 [patent_app_number] => 09/791288 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3560 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732219.pdf [firstpage_image] =>[orig_patent_app_number] => 09791288 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/791288
Dynamic allocation of devices to host controllers Feb 22, 2001 Issued
Array ( [id] => 1085004 [patent_doc_number] => 06834317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Network topology for food service equipment items' [patent_app_type] => B2 [patent_app_number] => 09/771432 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 2354 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/834/06834317.pdf [firstpage_image] =>[orig_patent_app_number] => 09771432 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/771432
Network topology for food service equipment items Jan 25, 2001 Issued
Array ( [id] => 7367285 [patent_doc_number] => 20040015617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Flexible network interfaces and flexible data clocking' [patent_app_type] => new [patent_app_number] => 09/770345 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015617.pdf [firstpage_image] =>[orig_patent_app_number] => 09770345 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/770345
Flexible network interfaces and flexible data clocking Jan 24, 2001 Abandoned
Array ( [id] => 6888611 [patent_doc_number] => 20010024066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Handheld device, smart card interface device (IFD) and data transmission method' [patent_app_type] => new [patent_app_number] => 09/761053 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4837 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20010024066.pdf [firstpage_image] =>[orig_patent_app_number] => 09761053 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/761053
Handheld device, smart card interface device (IFD) and data transmission method Jan 15, 2001 Abandoned
Array ( [id] => 1185759 [patent_doc_number] => 06745273 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Automatic deadlock prevention via arbitration switching' [patent_app_type] => B1 [patent_app_number] => 09/759921 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745273.pdf [firstpage_image] =>[orig_patent_app_number] => 09759921 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/759921
Automatic deadlock prevention via arbitration switching Jan 11, 2001 Issued
Array ( [id] => 1185752 [patent_doc_number] => 06745269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'Method and apparatus for preservation of data structures for hardware components discovery and initialization' [patent_app_type] => B2 [patent_app_number] => 09/758736 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745269.pdf [firstpage_image] =>[orig_patent_app_number] => 09758736 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758736
Method and apparatus for preservation of data structures for hardware components discovery and initialization Jan 10, 2001 Issued
Array ( [id] => 6880994 [patent_doc_number] => 20010032282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Bus protocol independent method and structure for managing transaction priority, ordering and deadlocks in a multi-processing system' [patent_app_type] => new [patent_app_number] => 09/758855 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032282.pdf [firstpage_image] =>[orig_patent_app_number] => 09758855 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758855
Bus protocol independent method and structure for managing transaction priority, ordering and deadlocks in a multi-processing system Jan 10, 2001 Issued
Array ( [id] => 6889873 [patent_doc_number] => 20010025328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Multiple memory coherence groups in a single system and method therefor' [patent_app_type] => new [patent_app_number] => 09/758856 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5407 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20010025328.pdf [firstpage_image] =>[orig_patent_app_number] => 09758856 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758856
Multiple memory coherence groups in a single system and method therefor Jan 10, 2001 Issued
Array ( [id] => 6648130 [patent_doc_number] => 20020087774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Method and apparatus for avoiding race condition with edge-triggered interrupts' [patent_app_type] => new [patent_app_number] => 09/752042 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1810 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087774.pdf [firstpage_image] =>[orig_patent_app_number] => 09752042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752042
Method and apparatus for avoiding race condition with edge-triggered interrupts Dec 28, 2000 Issued
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