Search

William B. Chou

Examiner (ID: 15166, Phone: (571)270-3367 , Office: P/3779 )

Most Active Art Unit
3795
Art Unit(s)
3779, 3795
Total Applications
590
Issued Applications
403
Pending Applications
53
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1508977 [patent_doc_number] => 06467010 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Method and arrangement for passing data between a reference chip and an external bus' [patent_app_type] => B1 [patent_app_number] => 09/513009 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5361 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467010.pdf [firstpage_image] =>[orig_patent_app_number] => 09513009 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/513009
Method and arrangement for passing data between a reference chip and an external bus Feb 24, 2000 Issued
Array ( [id] => 1109692 [patent_doc_number] => 06813669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Agent provided by USB device for executing USB device dependent program in USB host' [patent_app_type] => B1 [patent_app_number] => 09/512200 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2198 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813669.pdf [firstpage_image] =>[orig_patent_app_number] => 09512200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/512200
Agent provided by USB device for executing USB device dependent program in USB host Feb 23, 2000 Issued
Array ( [id] => 1429067 [patent_doc_number] => 06529978 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Computer input/output (I/O) interface with dynamic I/O adaptor processor bindings' [patent_app_type] => B1 [patent_app_number] => 09/511506 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529978.pdf [firstpage_image] =>[orig_patent_app_number] => 09511506 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511506
Computer input/output (I/O) interface with dynamic I/O adaptor processor bindings Feb 22, 2000 Issued
Array ( [id] => 950034 [patent_doc_number] => 06963944 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'Method and device for the serial transmission of data' [patent_app_type] => utility [patent_app_number] => 09/505895 [patent_app_country] => US [patent_app_date] => 2000-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6660 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963944.pdf [firstpage_image] =>[orig_patent_app_number] => 09505895 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505895
Method and device for the serial transmission of data Feb 16, 2000 Issued
Array ( [id] => 1221667 [patent_doc_number] => 06708236 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Bus control apparatus' [patent_app_type] => B1 [patent_app_number] => 09/492518 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 108 [patent_figures_cnt] => 116 [patent_no_of_words] => 40603 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/708/06708236.pdf [firstpage_image] =>[orig_patent_app_number] => 09492518 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492518
Bus control apparatus Jan 26, 2000 Issued
Array ( [id] => 7633105 [patent_doc_number] => 06658515 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Background execution of universal serial bus transactions' [patent_app_type] => B1 [patent_app_number] => 09/491177 [patent_app_country] => US [patent_app_date] => 2000-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4565 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658515.pdf [firstpage_image] =>[orig_patent_app_number] => 09491177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/491177
Background execution of universal serial bus transactions Jan 24, 2000 Issued
Array ( [id] => 1279316 [patent_doc_number] => 06654832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method of initializing a processor and computer system' [patent_app_type] => B1 [patent_app_number] => 09/493441 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3099 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654832.pdf [firstpage_image] =>[orig_patent_app_number] => 09493441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/493441
Method of initializing a processor and computer system Jan 17, 2000 Issued
Array ( [id] => 1573739 [patent_doc_number] => 06499080 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Post write buffer for a dual clock system' [patent_app_type] => B1 [patent_app_number] => 09/478846 [patent_app_country] => US [patent_app_date] => 2000-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5078 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499080.pdf [firstpage_image] =>[orig_patent_app_number] => 09478846 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/478846
Post write buffer for a dual clock system Jan 6, 2000 Issued
Array ( [id] => 645472 [patent_doc_number] => 07124221 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-17 [patent_title] => 'Low latency multi-level communication interface' [patent_app_type] => utility [patent_app_number] => 09/478916 [patent_app_country] => US [patent_app_date] => 2000-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 85 [patent_no_of_words] => 34391 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124221.pdf [firstpage_image] =>[orig_patent_app_number] => 09478916 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/478916
Low latency multi-level communication interface Jan 5, 2000 Issued
Array ( [id] => 1365097 [patent_doc_number] => 06581127 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Framework and method for inter-element channel transmission' [patent_app_type] => B1 [patent_app_number] => 09/477286 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3528 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581127.pdf [firstpage_image] =>[orig_patent_app_number] => 09477286 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477286
Framework and method for inter-element channel transmission Jan 3, 2000 Issued
Array ( [id] => 945749 [patent_doc_number] => 06968412 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-22 [patent_title] => 'Method and apparatus for interrupt controller data re-direction' [patent_app_type] => utility [patent_app_number] => 09/476443 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2392 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/968/06968412.pdf [firstpage_image] =>[orig_patent_app_number] => 09476443 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476443
Method and apparatus for interrupt controller data re-direction Dec 29, 1999 Issued
Array ( [id] => 1279351 [patent_doc_number] => 06654837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Dynamic priority external transaction system' [patent_app_type] => B1 [patent_app_number] => 09/474011 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3597 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654837.pdf [firstpage_image] =>[orig_patent_app_number] => 09474011 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474011
Dynamic priority external transaction system Dec 27, 1999 Issued
Array ( [id] => 1129535 [patent_doc_number] => 06795881 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-21 [patent_title] => 'Physical layer and data link interface with ethernet pre-negotiation' [patent_app_type] => B1 [patent_app_number] => 09/471200 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4886 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795881.pdf [firstpage_image] =>[orig_patent_app_number] => 09471200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471200
Physical layer and data link interface with ethernet pre-negotiation Dec 22, 1999 Issued
Array ( [id] => 1308506 [patent_doc_number] => 06629174 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Synchronization using bus arbitration control for system analysis' [patent_app_type] => B1 [patent_app_number] => 09/460876 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 9893 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629174.pdf [firstpage_image] =>[orig_patent_app_number] => 09460876 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460876
Synchronization using bus arbitration control for system analysis Dec 13, 1999 Issued
Array ( [id] => 1602206 [patent_doc_number] => 06493784 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Communication device, multiple bus control device and LSI for controlling multiple bus' [patent_app_type] => B1 [patent_app_number] => 09/454858 [patent_app_country] => US [patent_app_date] => 1999-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 32 [patent_no_of_words] => 11870 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493784.pdf [firstpage_image] =>[orig_patent_app_number] => 09454858 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/454858
Communication device, multiple bus control device and LSI for controlling multiple bus Dec 6, 1999 Issued
Array ( [id] => 1595816 [patent_doc_number] => 06484222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'System for incorporating multiple expansion slots in a variable speed peripheral bus' [patent_app_type] => B1 [patent_app_number] => 09/455048 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5245 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484222.pdf [firstpage_image] =>[orig_patent_app_number] => 09455048 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/455048
System for incorporating multiple expansion slots in a variable speed peripheral bus Dec 5, 1999 Issued
Array ( [id] => 4381799 [patent_doc_number] => 06256742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Information processing apparatus having a power saving function' [patent_app_type] => 1 [patent_app_number] => 9/455364 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9499 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256742.pdf [firstpage_image] =>[orig_patent_app_number] => 455364 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/455364
Information processing apparatus having a power saving function Dec 5, 1999 Issued
Array ( [id] => 1395091 [patent_doc_number] => 06567876 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Docking PCI to PCI bridge using IEEE 1394 link' [patent_app_type] => B1 [patent_app_number] => 09/454957 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11701 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567876.pdf [firstpage_image] =>[orig_patent_app_number] => 09454957 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/454957
Docking PCI to PCI bridge using IEEE 1394 link Dec 2, 1999 Issued
Array ( [id] => 1444041 [patent_doc_number] => 06496890 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Bus hang prevention and recovery for data communication systems employing a shared bus interface with multiple bus masters' [patent_app_type] => B1 [patent_app_number] => 09/454681 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496890.pdf [firstpage_image] =>[orig_patent_app_number] => 09454681 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/454681
Bus hang prevention and recovery for data communication systems employing a shared bus interface with multiple bus masters Dec 2, 1999 Issued
Array ( [id] => 6661122 [patent_doc_number] => 20030135766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Method and apparatus to control computer system power' [patent_app_type] => new [patent_app_number] => 09/453656 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3233 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20030135766.pdf [firstpage_image] =>[orig_patent_app_number] => 09453656 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/453656
Method and apparatus to control computer system power Dec 2, 1999 Abandoned
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