
William B. Partridge
Examiner (ID: 7131, Phone: (571)270-1402 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2812, 2183 |
| Total Applications | 514 |
| Issued Applications | 410 |
| Pending Applications | 4 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10630445
[patent_doc_number] => 09348595
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-05-24
[patent_title] => 'Run-time code parallelization with continuous monitoring of repetitive instruction sequences'
[patent_app_type] => utility
[patent_app_number] => 14/578516
[patent_app_country] => US
[patent_app_date] => 2014-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 6385
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14578516
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/578516 | Run-time code parallelization with continuous monitoring of repetitive instruction sequences | Dec 21, 2014 | Issued |
Array
(
[id] => 10258092
[patent_doc_number] => 20150143089
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-21
[patent_title] => 'SYSTEM PERFORMANCE ENHANCEMENT WITH SMI ON MULTI-CORE SYSTEMS'
[patent_app_type] => utility
[patent_app_number] => 14/549272
[patent_app_country] => US
[patent_app_date] => 2014-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6645
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549272
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/549272 | System performance enhancement with SMI on multi-core systems | Nov 19, 2014 | Issued |
Array
(
[id] => 12173780
[patent_doc_number] => 09891923
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-13
[patent_title] => 'Loop predictor-directed loop buffer'
[patent_app_type] => utility
[patent_app_number] => 14/534841
[patent_app_country] => US
[patent_app_date] => 2014-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 8450
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14534841
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/534841 | Loop predictor-directed loop buffer | Nov 5, 2014 | Issued |
Array
(
[id] => 10778553
[patent_doc_number] => 20160124709
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-05
[patent_title] => 'FAST, ENERGY-EFFICIENT EXPONENTIAL COMPUTATIONS IN SIMD ARCHITECTURES'
[patent_app_type] => utility
[patent_app_number] => 14/532312
[patent_app_country] => US
[patent_app_date] => 2014-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6517
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14532312
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/532312 | FAST, ENERGY-EFFICIENT EXPONENTIAL COMPUTATIONS IN SIMD ARCHITECTURES | Nov 3, 2014 | Abandoned |
Array
(
[id] => 12169141
[patent_doc_number] => 09887918
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-02-06
[patent_title] => 'Intelligent packet data register file that stalls picoengine and retrieves data from a larger buffer'
[patent_app_type] => utility
[patent_app_number] => 14/530762
[patent_app_country] => US
[patent_app_date] => 2014-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 39
[patent_no_of_words] => 18879
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14530762
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/530762 | Intelligent packet data register file that stalls picoengine and retrieves data from a larger buffer | Nov 1, 2014 | Issued |
Array
(
[id] => 11752260
[patent_doc_number] => 09710272
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-18
[patent_title] => 'Computer processor with generation renaming'
[patent_app_type] => utility
[patent_app_number] => 14/530370
[patent_app_country] => US
[patent_app_date] => 2014-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 22870
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14530370
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/530370 | Computer processor with generation renaming | Oct 30, 2014 | Issued |
Array
(
[id] => 10724425
[patent_doc_number] => 20160070573
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-10
[patent_title] => 'CONDITION CODE GENERATION'
[patent_app_type] => utility
[patent_app_number] => 14/514546
[patent_app_country] => US
[patent_app_date] => 2014-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5926
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14514546
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/514546 | Inference based condition code generation | Oct 14, 2014 | Issued |
Array
(
[id] => 10731685
[patent_doc_number] => 20160077836
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-17
[patent_title] => 'PREDICTING LITERAL LOAD VALUES USING A LITERAL LOAD PREDICTION TABLE, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA'
[patent_app_type] => utility
[patent_app_number] => 14/484659
[patent_app_country] => US
[patent_app_date] => 2014-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7604
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14484659
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/484659 | PREDICTING LITERAL LOAD VALUES USING A LITERAL LOAD PREDICTION TABLE, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA | Sep 11, 2014 | Abandoned |
Array
(
[id] => 10210635
[patent_doc_number] => 20150095626
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-02
[patent_title] => 'TRACE METHOD AND INFORMATION PROCESSING APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 14/483750
[patent_app_country] => US
[patent_app_date] => 2014-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 13258
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483750
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/483750 | Trace method and information processing apparatus | Sep 10, 2014 | Issued |
Array
(
[id] => 11550441
[patent_doc_number] => 09619289
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-11
[patent_title] => 'Workload optimized server for intelligent algorithm trading platforms'
[patent_app_type] => utility
[patent_app_number] => 14/483597
[patent_app_country] => US
[patent_app_date] => 2014-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 7553
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483597
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/483597 | Workload optimized server for intelligent algorithm trading platforms | Sep 10, 2014 | Issued |
Array
(
[id] => 10724428
[patent_doc_number] => 20160070576
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-10
[patent_title] => 'SPECULATIVE REGISTER FILE READ SUPPRESSION'
[patent_app_type] => utility
[patent_app_number] => 14/482146
[patent_app_country] => US
[patent_app_date] => 2014-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3335
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14482146
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/482146 | Speculative register file read suppression | Sep 9, 2014 | Issued |
Array
(
[id] => 10724424
[patent_doc_number] => 20160070572
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-10
[patent_title] => 'CONDITION CODE GENERATION'
[patent_app_type] => utility
[patent_app_number] => 14/482042
[patent_app_country] => US
[patent_app_date] => 2014-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5926
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14482042
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/482042 | Inference based condition code generation | Sep 9, 2014 | Issued |
Array
(
[id] => 10702249
[patent_doc_number] => 20160048396
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-18
[patent_title] => 'CENTRAL PROCESSOR-COPROCESSOR SYNCHRONIZATION'
[patent_app_type] => utility
[patent_app_number] => 14/459416
[patent_app_country] => US
[patent_app_date] => 2014-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4278
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459416
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/459416 | System and method for synchronizing instruction execution between a central processor and a coprocessor | Aug 13, 2014 | Issued |
Array
(
[id] => 11359052
[patent_doc_number] => 09535705
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-01-03
[patent_title] => 'Flexible hardware programmable scalable parallel processor'
[patent_app_type] => utility
[patent_app_number] => 14/458972
[patent_app_country] => US
[patent_app_date] => 2014-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2316
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458972
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/458972 | Flexible hardware programmable scalable parallel processor | Aug 12, 2014 | Issued |
Array
(
[id] => 10439187
[patent_doc_number] => 20150324198
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-12
[patent_title] => 'CONTROL FLOW WITHOUT BRANCHING'
[patent_app_type] => utility
[patent_app_number] => 14/458165
[patent_app_country] => US
[patent_app_date] => 2014-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 16291
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458165
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/458165 | Control flow in a thread-based environment without branching | Aug 11, 2014 | Issued |
Array
(
[id] => 9866654
[patent_doc_number] => 20150046673
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-12
[patent_title] => 'VECTOR PROCESSOR'
[patent_app_type] => utility
[patent_app_number] => 14/457929
[patent_app_country] => US
[patent_app_date] => 2014-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10459
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14457929
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/457929 | Variable-length instruction buffer management | Aug 11, 2014 | Issued |
Array
(
[id] => 9866656
[patent_doc_number] => 20150046675
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-12
[patent_title] => 'APPARATUS, SYSTEMS, AND METHODS FOR LOW POWER COMPUTATIONAL IMAGING'
[patent_app_type] => utility
[patent_app_number] => 14/458052
[patent_app_country] => US
[patent_app_date] => 2014-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 19833
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458052
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/458052 | Apparatus, systems, and methods for low power computational imaging | Aug 11, 2014 | Issued |
Array
(
[id] => 10610025
[patent_doc_number] => 09330058
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-03
[patent_title] => 'Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements'
[patent_app_type] => utility
[patent_app_number] => 14/453947
[patent_app_country] => US
[patent_app_date] => 2014-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 17405
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14453947
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/453947 | Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements | Aug 6, 2014 | Issued |
Array
(
[id] => 10695799
[patent_doc_number] => 20160041945
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-11
[patent_title] => 'INSTRUCTION AND LOGIC FOR STORE BROADCAST'
[patent_app_type] => utility
[patent_app_number] => 14/453341
[patent_app_country] => US
[patent_app_date] => 2014-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 25012
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14453341
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/453341 | Instruction and logic for store broadcast and power management | Aug 5, 2014 | Issued |
Array
(
[id] => 11577312
[patent_doc_number] => 09632569
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-25
[patent_title] => 'Directed event signaling for multiprocessor systems'
[patent_app_type] => utility
[patent_app_number] => 14/451628
[patent_app_country] => US
[patent_app_date] => 2014-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 13467
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14451628
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/451628 | Directed event signaling for multiprocessor systems | Aug 4, 2014 | Issued |