Search

William B. Partridge

Examiner (ID: 11002, Phone: (571)270-1402 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2812, 2183
Total Applications
515
Issued Applications
410
Pending Applications
5
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10493918 [patent_doc_number] => 20150378940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'TRANSACTIONAL EXECUTION ENABLED SUPERVISOR CALL INTERRUPTION WHILE IN TX MODE' [patent_app_type] => utility [patent_app_number] => 14/316894 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 19708 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14316894 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/316894
Transactional execution enabled supervisor call interruption while in TX mode Jun 26, 2014 Issued
Array ( [id] => 10493708 [patent_doc_number] => 20150378730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'SYSTEM ON A CHIP WITH MANAGING PROCESSOR AND METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 14/316876 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6219 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14316876 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/316876
System on a chip with managing processor and method therefor Jun 26, 2014 Issued
Array ( [id] => 10493716 [patent_doc_number] => 20150378738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'ACCURATE TRACKING OF TRANSACTIONAL READ AND WRITE SETS WITH SPECULATION' [patent_app_type] => utility [patent_app_number] => 14/317371 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 24779 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317371 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/317371
Accurate tracking of transactional read and write sets with speculation Jun 26, 2014 Issued
Array ( [id] => 9604822 [patent_doc_number] => 20140201503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 14/215412 [patent_app_country] => US [patent_app_date] => 2014-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 30644 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14215412 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/215412
Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture Mar 16, 2014 Issued
Array ( [id] => 9746882 [patent_doc_number] => 20140282601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD FOR DEPENDENCY BROADCASTING THROUGH A BLOCK ORGANIZED SOURCE VIEW DATA STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/216859 [patent_app_country] => US [patent_app_date] => 2014-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 9844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14216859 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/216859
Method for dependency broadcasting through a block organized source view data structure Mar 16, 2014 Issued
Array ( [id] => 9745707 [patent_doc_number] => 20140281426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD FOR POPULATING A SOURCE VIEW DATA STRUCTURE BY USING REGISTER TEMPLATE SNAPSHOTS' [patent_app_type] => utility [patent_app_number] => 14/213115 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 9757 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14213115 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/213115
Method for populating a source view data structure by using register template snapshots Mar 13, 2014 Issued
Array ( [id] => 9745709 [patent_doc_number] => 20140281428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD FOR POPULATING REGISTER VIEW DATA STRUCTURE BY USING REGISTER TEMPLATE SNAPSHOTS' [patent_app_type] => utility [patent_app_number] => 14/213854 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 9761 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14213854 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/213854
Method for populating register view data structure by using register template snapshots Mar 13, 2014 Issued
Array ( [id] => 10914368 [patent_doc_number] => 20140317387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'METHOD FOR PERFORMING DUAL DISPATCH OF BLOCKS AND HALF BLOCKS' [patent_app_type] => utility [patent_app_number] => 14/213218 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 9706 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14213218 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/213218
Method for performing dual dispatch of blocks and half blocks Mar 13, 2014 Issued
Array ( [id] => 12100986 [patent_doc_number] => 09858080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Method for implementing a reduced size register view data structure in a microprocessor' [patent_app_type] => utility [patent_app_number] => 14/213692 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9774 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14213692 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/213692
Method for implementing a reduced size register view data structure in a microprocessor Mar 13, 2014 Issued
Array ( [id] => 10680325 [patent_doc_number] => 20160026469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'DATA CACHE SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/775517 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17479 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14775517 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/775517
Data cache system and method Mar 13, 2014 Issued
Array ( [id] => 14250111 [patent_doc_number] => 10275255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Method for dependency broadcasting through a source organized source view data structure [patent_app_type] => utility [patent_app_number] => 14/213135 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14213135 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/213135
Method for dependency broadcasting through a source organized source view data structure Mar 13, 2014 Issued
Array ( [id] => 12046328 [patent_doc_number] => 09823930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Method for emulating a guest centralized flag architecture by using a native distributed flag architecture' [patent_app_type] => utility [patent_app_number] => 14/213730 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9738 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14213730 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/213730
Method for emulating a guest centralized flag architecture by using a native distributed flag architecture Mar 13, 2014 Issued
Array ( [id] => 11795721 [patent_doc_number] => 09405546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-02 [patent_title] => 'Apparatus and method for non-blocking execution of static scheduled processor' [patent_app_type] => utility [patent_app_number] => 14/199154 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6369 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14199154 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/199154
Apparatus and method for non-blocking execution of static scheduled processor Mar 5, 2014 Issued
Array ( [id] => 9548608 [patent_doc_number] => 20140173256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'PROCESSOR CONFIGURED FOR OPERATION WITH MULTIPLE OPERATION CODES PER INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/186707 [patent_app_country] => US [patent_app_date] => 2014-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4827 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14186707 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/186707
PROCESSOR CONFIGURED FOR OPERATION WITH MULTIPLE OPERATION CODES PER INSTRUCTION Feb 20, 2014 Abandoned
Array ( [id] => 11285593 [patent_doc_number] => 09501448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Execution engine for executing single assignment programs with affine dependencies' [patent_app_type] => utility [patent_app_number] => 14/185841 [patent_app_country] => US [patent_app_date] => 2014-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8073 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14185841 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/185841
Execution engine for executing single assignment programs with affine dependencies Feb 19, 2014 Issued
Array ( [id] => 17194819 [patent_doc_number] => 11163572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Memory systems and memory control methods [patent_app_type] => utility [patent_app_number] => 14/172806 [patent_app_country] => US [patent_app_date] => 2014-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4645 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14172806 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/172806
Memory systems and memory control methods Feb 3, 2014 Issued
Array ( [id] => 10027694 [patent_doc_number] => 09069595 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-30 [patent_title] => 'Systems and methods for overseas desktop software' [patent_app_type] => utility [patent_app_number] => 14/159771 [patent_app_country] => US [patent_app_date] => 2014-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6388 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159771 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159771
Systems and methods for overseas desktop software Jan 20, 2014 Issued
Array ( [id] => 12213679 [patent_doc_number] => 09910483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Distribution of tasks among asymmetric processing elements' [patent_app_type] => utility [patent_app_number] => 14/154517 [patent_app_country] => US [patent_app_date] => 2014-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5020 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14154517 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/154517
Distribution of tasks among asymmetric processing elements Jan 13, 2014 Issued
Array ( [id] => 9410148 [patent_doc_number] => 20140101400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'STORE PERIPHERAL COMPONENT INTERCONNECT (PCI) FUNCTION CONTROLS INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/102952 [patent_app_country] => US [patent_app_date] => 2013-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 19212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14102952 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/102952
Store peripheral component interconnect (PCI) function controls instruction Dec 10, 2013 Issued
Array ( [id] => 9398514 [patent_doc_number] => 20140095920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'Variable clocked serial array processor' [patent_app_type] => utility [patent_app_number] => 14/100344 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8130 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100344 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/100344
Variable clocked serial array processor Dec 8, 2013 Issued
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