Search

William B. Partridge

Examiner (ID: 11002, Phone: (571)270-1402 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2812, 2183
Total Applications
515
Issued Applications
410
Pending Applications
5
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7682582 [patent_doc_number] => 20100241829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'HARDWARE SWITCH AND DISTRIBUTED PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/726456 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 10486 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20100241829.pdf [firstpage_image] =>[orig_patent_app_number] => 12726456 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/726456
HARDWARE SWITCH AND DISTRIBUTED PROCESSING SYSTEM Mar 17, 2010 Abandoned
Array ( [id] => 6240911 [patent_doc_number] => 20100268913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'LITHOGRAPHIC APPARATUS, CONTROL SYSTEM, MULTI-CORE PROCESSOR, AND A METHOD TO START TASKS ON A MULTI-CORE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/726396 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6145 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20100268913.pdf [firstpage_image] =>[orig_patent_app_number] => 12726396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/726396
LITHOGRAPHIC APPARATUS, CONTROL SYSTEM, MULTI-CORE PROCESSOR, AND A METHOD TO START TASKS ON A MULTI-CORE PROCESSOR Mar 17, 2010 Abandoned
Array ( [id] => 10196629 [patent_doc_number] => 09225547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Apparatus, method, and medium for controlling transmission of data' [patent_app_type] => utility [patent_app_number] => 12/724314 [patent_app_country] => US [patent_app_date] => 2010-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 13868 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12724314 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/724314
Apparatus, method, and medium for controlling transmission of data Mar 14, 2010 Issued
Array ( [id] => 10524602 [patent_doc_number] => 09251117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Reconfigurable circuit with suspension control circuit' [patent_app_type] => utility [patent_app_number] => 12/723320 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7587 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12723320 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/723320
Reconfigurable circuit with suspension control circuit Mar 11, 2010 Issued
Array ( [id] => 6301941 [patent_doc_number] => 20100161940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS' [patent_app_type] => utility [patent_app_number] => 12/719394 [patent_app_country] => US [patent_app_date] => 2010-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8506 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20100161940.pdf [firstpage_image] =>[orig_patent_app_number] => 12719394 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/719394
ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS Mar 7, 2010 Abandoned
Array ( [id] => 6464437 [patent_doc_number] => 20100146315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'Software Selectable Adjustment of SIMD Parallelism' [patent_app_type] => utility [patent_app_number] => 12/706987 [patent_app_country] => US [patent_app_date] => 2010-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20100146315.pdf [firstpage_image] =>[orig_patent_app_number] => 12706987 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/706987
Software selectable adjustment of SIMD parallelism Feb 16, 2010 Issued
Array ( [id] => 9314908 [patent_doc_number] => 08656143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Variable clocked heterogeneous serial array processor' [patent_app_type] => utility [patent_app_number] => 12/699548 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 8116 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12699548 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/699548
Variable clocked heterogeneous serial array processor Feb 2, 2010 Issued
Array ( [id] => 10885505 [patent_doc_number] => 08909908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Microprocessor that refrains from executing a mispredicted branch in the presence of an older unretired cache-missing load instruction' [patent_app_type] => utility [patent_app_number] => 12/582975 [patent_app_country] => US [patent_app_date] => 2009-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5593 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12582975 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/582975
Microprocessor that refrains from executing a mispredicted branch in the presence of an older unretired cache-missing load instruction Oct 20, 2009 Issued
Array ( [id] => 5996305 [patent_doc_number] => 20110016296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'APPARATUS AND METHOD FOR EXECUTING FAST BIT SCAN FORWARD/REVERSE (BSR/BSF) INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 12/582907 [patent_app_country] => US [patent_app_date] => 2009-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3744 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20110016296.pdf [firstpage_image] =>[orig_patent_app_number] => 12582907 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/582907
Apparatus and method for executing fast bit scan forward/reverse (BSR/BSF) instructions Oct 20, 2009 Issued
Array ( [id] => 6040609 [patent_doc_number] => 20110093658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'CLASSIFYING AND SEGREGATING BRANCH TARGETS' [patent_app_type] => utility [patent_app_number] => 12/581878 [patent_app_country] => US [patent_app_date] => 2009-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20110093658.pdf [firstpage_image] =>[orig_patent_app_number] => 12581878 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/581878
CLASSIFYING AND SEGREGATING BRANCH TARGETS Oct 18, 2009 Abandoned
Array ( [id] => 7679643 [patent_doc_number] => 20100106944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-29 [patent_title] => 'Data processing apparatus and method for performing rearrangement operations' [patent_app_type] => utility [patent_app_number] => 12/588412 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 59 [patent_no_of_words] => 32736 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20100106944.pdf [firstpage_image] =>[orig_patent_app_number] => 12588412 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/588412
Data processing apparatus and method for performing N-way interleaving and de-interleaving operations where N is an odd plural number Oct 13, 2009 Issued
Array ( [id] => 7681112 [patent_doc_number] => 20100023696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'Methods and System for Resolving Simultaneous Predicted Branch Instructions' [patent_app_type] => utility [patent_app_number] => 12/569365 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5562 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023696.pdf [firstpage_image] =>[orig_patent_app_number] => 12569365 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/569365
Methods and system for resolving simultaneous predicted branch instructions Sep 28, 2009 Issued
Array ( [id] => 8251253 [patent_doc_number] => 20120155570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'DEVICE AND METHOD FOR PERFORMING BITWISE MANIPULATIONS' [patent_app_type] => utility [patent_app_number] => 13/392925 [patent_app_country] => US [patent_app_date] => 2009-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20120155570.pdf [firstpage_image] =>[orig_patent_app_number] => 13392925 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/392925
Device and method for performing conditional bitwise set/clear/toggle manipulations in a general purpose register Sep 23, 2009 Issued
Array ( [id] => 7684069 [patent_doc_number] => 20100122072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'Debugging system, debugging method, debugging control method, and debugging control program' [patent_app_type] => utility [patent_app_number] => 12/585693 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3882 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122072.pdf [firstpage_image] =>[orig_patent_app_number] => 12585693 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585693
Debugging system, debugging method, debugging control method, and debugging control program Sep 21, 2009 Abandoned
Array ( [id] => 8201760 [patent_doc_number] => 20120124336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'SIGNAL PROCESSING SYSTEM AND INTEGRATED CIRCUIT COMPRISING A PREFETCH MODULE AND METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/382796 [patent_app_country] => US [patent_app_date] => 2009-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4699 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124336.pdf [firstpage_image] =>[orig_patent_app_number] => 13382796 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/382796
Signal processing system and integrated circuit comprising a prefetch module and method therefor Jul 19, 2009 Issued
Array ( [id] => 5317615 [patent_doc_number] => 20090282213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/505128 [patent_app_country] => US [patent_app_date] => 2009-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11343 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282213.pdf [firstpage_image] =>[orig_patent_app_number] => 12505128 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/505128
SEMICONDUCTOR INTEGRATED CIRCUIT Jul 16, 2009 Abandoned
Array ( [id] => 6584760 [patent_doc_number] => 20100235610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'PROCESSING SYSTEM, PROCESSING APPARATUS AND COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/502751 [patent_app_country] => US [patent_app_date] => 2009-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8921 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20100235610.pdf [firstpage_image] =>[orig_patent_app_number] => 12502751 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/502751
PROCESSING SYSTEM, PROCESSING APPARATUS AND COMPUTER READABLE MEDIUM Jul 13, 2009 Abandoned
Array ( [id] => 8824088 [patent_doc_number] => 20130125133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'System and Method for Load Balancing of Fully Strict Thread-Level Parallel Programs' [patent_app_type] => utility [patent_app_number] => 12/475212 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 16919 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12475212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/475212
System and Method for Load Balancing of Fully Strict Thread-Level Parallel Programs May 28, 2009 Abandoned
Array ( [id] => 10517749 [patent_doc_number] => 09244797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Methods for managing performance states in an information handling system' [patent_app_type] => utility [patent_app_number] => 12/475063 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12475063 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/475063
Methods for managing performance states in an information handling system May 28, 2009 Issued
Array ( [id] => 6415945 [patent_doc_number] => 20100306779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'WORKFLOW MANAGEMENT SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/475045 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9496 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20100306779.pdf [firstpage_image] =>[orig_patent_app_number] => 12475045 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/475045
System and method for adjusting a number of processing modules based on processing load May 28, 2009 Issued
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