
William B. Partridge
Examiner (ID: 11002, Phone: (571)270-1402 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2812, 2183 |
| Total Applications | 515 |
| Issued Applications | 410 |
| Pending Applications | 5 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6240929
[patent_doc_number] => 20100268919
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-21
[patent_title] => 'METHOD AND STRUCTURE FOR SOLVING THE EVIL-TWIN PROBLEM'
[patent_app_type] => utility
[patent_app_number] => 12/426550
[patent_app_country] => US
[patent_app_date] => 2009-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4501
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0268/20100268919.pdf
[firstpage_image] =>[orig_patent_app_number] => 12426550
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/426550 | Method and structure for solving the evil-twin problem | Apr 19, 2009 | Issued |
Array
(
[id] => 10860702
[patent_doc_number] => 08886919
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-11
[patent_title] => 'Remote update programming idiom accelerator with allocated processor resources'
[patent_app_type] => utility
[patent_app_number] => 12/424952
[patent_app_country] => US
[patent_app_date] => 2009-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 45
[patent_no_of_words] => 24360
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 268
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12424952
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/424952 | Remote update programming idiom accelerator with allocated processor resources | Apr 15, 2009 | Issued |
Array
(
[id] => 6240933
[patent_doc_number] => 20100268921
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-21
[patent_title] => 'DATA COLLECTION PREFETCH DEVICE AND METHODS THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/423912
[patent_app_country] => US
[patent_app_date] => 2009-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3067
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0268/20100268921.pdf
[firstpage_image] =>[orig_patent_app_number] => 12423912
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/423912 | DATA COLLECTION PREFETCH DEVICE AND METHODS THEREOF | Apr 14, 2009 | Abandoned |
Array
(
[id] => 6533328
[patent_doc_number] => 20100262806
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-14
[patent_title] => 'Tracking Effective Addresses in an Out-of-Order Processor'
[patent_app_type] => utility
[patent_app_number] => 12/422595
[patent_app_country] => US
[patent_app_date] => 2009-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 12396
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0262/20100262806.pdf
[firstpage_image] =>[orig_patent_app_number] => 12422595
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/422595 | Tracking effective addresses in an out-of-order processor | Apr 12, 2009 | Issued |
Array
(
[id] => 6280896
[patent_doc_number] => 20100257341
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-07
[patent_title] => 'Selective Execution Dependency Matrix'
[patent_app_type] => utility
[patent_app_number] => 12/417801
[patent_app_country] => US
[patent_app_date] => 2009-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6541
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0257/20100257341.pdf
[firstpage_image] =>[orig_patent_app_number] => 12417801
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/417801 | Selective Execution Dependency Matrix | Apr 2, 2009 | Abandoned |
Array
(
[id] => 6280886
[patent_doc_number] => 20100257339
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-07
[patent_title] => 'Dependency Matrix with Improved Performance'
[patent_app_type] => utility
[patent_app_number] => 12/417831
[patent_app_country] => US
[patent_app_date] => 2009-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5673
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0257/20100257339.pdf
[firstpage_image] =>[orig_patent_app_number] => 12417831
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/417831 | Dependency Matrix with Improved Performance | Apr 2, 2009 | Abandoned |
Array
(
[id] => 10890608
[patent_doc_number] => 08914621
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-16
[patent_title] => 'Processing unit that detects manipulations thereof, device comprising two processing units, method for testing a processing unit and a device comprising two processing units'
[patent_app_type] => utility
[patent_app_number] => 12/417172
[patent_app_country] => US
[patent_app_date] => 2009-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 8081
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12417172
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/417172 | Processing unit that detects manipulations thereof, device comprising two processing units, method for testing a processing unit and a device comprising two processing units | Apr 1, 2009 | Issued |
Array
(
[id] => 7682370
[patent_doc_number] => 20100242041
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-23
[patent_title] => 'Real Time Multithreaded Scheduler and Scheduling Method'
[patent_app_type] => utility
[patent_app_number] => 12/405271
[patent_app_country] => US
[patent_app_date] => 2009-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8030
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0242/20100242041.pdf
[firstpage_image] =>[orig_patent_app_number] => 12405271
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/405271 | Real time multithreaded scheduler and scheduling method | Mar 16, 2009 | Issued |
Array
(
[id] => 5535486
[patent_doc_number] => 20090235274
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-17
[patent_title] => 'APPARATUS AND METHOD FOR TASK COUNT CONTROL'
[patent_app_type] => utility
[patent_app_number] => 12/405186
[patent_app_country] => US
[patent_app_date] => 2009-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8131
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20090235274.pdf
[firstpage_image] =>[orig_patent_app_number] => 12405186
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/405186 | Apparatus and method for dynamic control of the number of simultaneously executing tasks based on throughput | Mar 15, 2009 | Issued |
Array
(
[id] => 6588229
[patent_doc_number] => 20100235834
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-16
[patent_title] => 'PROVIDING A MANAGEMENT COMMUNICATION CHANNEL BETWEEN A SOFTWARE LAYER AND PLATFORM LAYER FOR HARDWARE MANAGEMENT CONTROL'
[patent_app_type] => utility
[patent_app_number] => 12/404387
[patent_app_country] => US
[patent_app_date] => 2009-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3717
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20100235834.pdf
[firstpage_image] =>[orig_patent_app_number] => 12404387
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/404387 | PROVIDING A MANAGEMENT COMMUNICATION CHANNEL BETWEEN A SOFTWARE LAYER AND PLATFORM LAYER FOR HARDWARE MANAGEMENT CONTROL | Mar 15, 2009 | Abandoned |
Array
(
[id] => 5370131
[patent_doc_number] => 20090307690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-10
[patent_title] => 'Managing Assignment of Partition Services to Virtual Input/Output Adapters'
[patent_app_type] => utility
[patent_app_number] => 12/403416
[patent_app_country] => US
[patent_app_date] => 2009-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7799
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0307/20090307690.pdf
[firstpage_image] =>[orig_patent_app_number] => 12403416
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/403416 | Managing assignment of partition services to virtual input/output adapters | Mar 12, 2009 | Issued |
Array
(
[id] => 6588303
[patent_doc_number] => 20100235840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-16
[patent_title] => 'POWER MANAGEMENT USING DYNAMIC APPLICATION SCHEDULING'
[patent_app_type] => utility
[patent_app_number] => 12/400845
[patent_app_country] => US
[patent_app_date] => 2009-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5542
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20100235840.pdf
[firstpage_image] =>[orig_patent_app_number] => 12400845
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/400845 | Power management using dynamic application scheduling | Mar 9, 2009 | Issued |
Array
(
[id] => 9187312
[patent_doc_number] => 08627313
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-01-07
[patent_title] => 'Virtual machine liveness determination'
[patent_app_type] => utility
[patent_app_number] => 12/400510
[patent_app_country] => US
[patent_app_date] => 2009-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6155
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12400510
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/400510 | Virtual machine liveness determination | Mar 8, 2009 | Issued |
Array
(
[id] => 7679425
[patent_doc_number] => 20100107162
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-29
[patent_title] => 'ROUTING ACROSS A VIRTUAL NETWORK'
[patent_app_type] => utility
[patent_app_number] => 12/400491
[patent_app_country] => US
[patent_app_date] => 2009-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 11038
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0107/20100107162.pdf
[firstpage_image] =>[orig_patent_app_number] => 12400491
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/400491 | Routing across a virtual network | Mar 8, 2009 | Issued |
Array
(
[id] => 5437550
[patent_doc_number] => 20090172137
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-02
[patent_title] => 'Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements'
[patent_app_type] => utility
[patent_app_number] => 12/399671
[patent_app_country] => US
[patent_app_date] => 2009-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 12191
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0172/20090172137.pdf
[firstpage_image] =>[orig_patent_app_number] => 12399671
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/399671 | Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements | Mar 5, 2009 | Issued |
Array
(
[id] => 6554670
[patent_doc_number] => 20100205411
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-12
[patent_title] => 'HANDLING COMPLEX REGEX PATTERNS STORAGE-EFFICIENTLY USING THE LOCAL RESULT PROCESSOR'
[patent_app_type] => utility
[patent_app_number] => 12/369440
[patent_app_country] => US
[patent_app_date] => 2009-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4677
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20100205411.pdf
[firstpage_image] =>[orig_patent_app_number] => 12369440
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/369440 | Handling complex regex patterns storage-efficiently using the local result processor | Feb 10, 2009 | Issued |
Array
(
[id] => 10854143
[patent_doc_number] => 08880854
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-04
[patent_title] => 'Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register'
[patent_app_type] => utility
[patent_app_number] => 12/369132
[patent_app_country] => US
[patent_app_date] => 2009-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 6111
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12369132
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/369132 | Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register | Feb 10, 2009 | Issued |
Array
(
[id] => 5475864
[patent_doc_number] => 20090249030
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'Multiprocessor System Having Direct Transfer Function for Program Status Information in Multilink Architecture'
[patent_app_type] => utility
[patent_app_number] => 12/368770
[patent_app_country] => US
[patent_app_date] => 2009-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 9471
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0249/20090249030.pdf
[firstpage_image] =>[orig_patent_app_number] => 12368770
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/368770 | Multiprocessor system having direct transfer function for program status information in multilink architecture | Feb 9, 2009 | Issued |
Array
(
[id] => 6554468
[patent_doc_number] => 20100205400
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-12
[patent_title] => 'EXECUTING ROUTINES BETWEEN AN EMULATED OPERATING SYSTEM AND A HOST OPERATING SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 12/367858
[patent_app_country] => US
[patent_app_date] => 2009-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5720
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20100205400.pdf
[firstpage_image] =>[orig_patent_app_number] => 12367858
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/367858 | EXECUTING ROUTINES BETWEEN AN EMULATED OPERATING SYSTEM AND A HOST OPERATING SYSTEM | Feb 8, 2009 | Abandoned |
Array
(
[id] => 10630449
[patent_doc_number] => 09348600
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-24
[patent_title] => 'Prioritising of instruction fetching in microprocessor systems'
[patent_app_type] => utility
[patent_app_number] => 12/322942
[patent_app_country] => US
[patent_app_date] => 2009-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4410
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12322942
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/322942 | Prioritising of instruction fetching in microprocessor systems | Feb 8, 2009 | Issued |