Search

William B. Partridge

Examiner (ID: 7131, Phone: (571)270-1402 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2812, 2183
Total Applications
514
Issued Applications
410
Pending Applications
4
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17238285 [patent_doc_number] => 11182164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-23 [patent_title] => Pairing issue queues for complex instructions and instruction fusion [patent_app_type] => utility [patent_app_number] => 16/936924 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936924 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936924
Pairing issue queues for complex instructions and instruction fusion Jul 22, 2020 Issued
Array ( [id] => 18386094 [patent_doc_number] => 11656875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Method and system for instruction block to execution unit grouping [patent_app_type] => utility [patent_app_number] => 16/928970 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9544 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928970 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/928970
Method and system for instruction block to execution unit grouping Jul 13, 2020 Issued
Array ( [id] => 17977332 [patent_doc_number] => 11494192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Pipeline including separate hardware data paths for different instruction types [patent_app_type] => utility [patent_app_number] => 16/860842 [patent_app_country] => US [patent_app_date] => 2020-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7476 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860842 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/860842
Pipeline including separate hardware data paths for different instruction types Apr 27, 2020 Issued
Array ( [id] => 17157833 [patent_doc_number] => 20210318884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => PROVIDING EXCEPTION STACK MANAGEMENT USING STACK PANIC FAULT EXCEPTIONS IN PROCESSOR-BASED DEVICES [patent_app_type] => utility [patent_app_number] => 16/843389 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843389 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/843389
Providing exception stack management using stack panic fault exceptions in processor-based devices Apr 7, 2020 Issued
Array ( [id] => 17252838 [patent_doc_number] => 11188327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Memory lookup computing mechanisms [patent_app_type] => utility [patent_app_number] => 16/823153 [patent_app_country] => US [patent_app_date] => 2020-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5760 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16823153 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/823153
Memory lookup computing mechanisms Mar 17, 2020 Issued
Array ( [id] => 16077359 [patent_doc_number] => 20200192666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => VARIABLE-LENGTH INSTRUCTION BUFFER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/797881 [patent_app_country] => US [patent_app_date] => 2020-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797881 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/797881
Variable-length instruction buffer management Feb 20, 2020 Issued
Array ( [id] => 17252854 [patent_doc_number] => 11188343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Apparatus, systems, and methods for low power computational imaging [patent_app_type] => utility [patent_app_number] => 16/719484 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 19361 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719484 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719484
Apparatus, systems, and methods for low power computational imaging Dec 17, 2019 Issued
Array ( [id] => 15561377 [patent_doc_number] => 20200065100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => APPARATUS AND METHOD FOR LOOP FLATTENING AND REDUCTION IN A SINGLE INSTRUCTION MULTIPLE DATA (SIMD) PIPELINE [patent_app_type] => utility [patent_app_number] => 16/554169 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16554169 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/554169
Apparatus and method for loop flattening and reduction in a single instruction multiple data (SIMD) pipeline Aug 27, 2019 Issued
Array ( [id] => 17121097 [patent_doc_number] => 11132231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Reconfiguring processing groups for cascading data workloads [patent_app_type] => utility [patent_app_number] => 16/536734 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16536734 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/536734
Reconfiguring processing groups for cascading data workloads Aug 8, 2019 Issued
Array ( [id] => 15151785 [patent_doc_number] => 20190354370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => COMBINING STATES OF MULTIPLE THREADS IN A MULTI-THREADED PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/529122 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529122 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/529122
Combining states of multiple threads in a multi threaded processor Jul 31, 2019 Issued
Array ( [id] => 15121013 [patent_doc_number] => 20190347140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => SYNCHRONIZATION WITH A HOST PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/514311 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/514311
Synchronization with a host processor Jul 16, 2019 Issued
Array ( [id] => 16986900 [patent_doc_number] => 11074072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Compute optimizations for neural networks using bipolar binary weight [patent_app_type] => utility [patent_app_number] => 16/505012 [patent_app_country] => US [patent_app_date] => 2019-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 46 [patent_no_of_words] => 32072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16505012 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/505012
Compute optimizations for neural networks using bipolar binary weight Jul 7, 2019 Issued
Array ( [id] => 14966747 [patent_doc_number] => 20190310852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => DECOUPLED PROCESSOR INSTRUCTION WINDOW AND OPERAND BUFFER [patent_app_type] => utility [patent_app_number] => 16/450172 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450172 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/450172
Decoupled processor instruction window and operand buffer Jun 23, 2019 Issued
Array ( [id] => 16972293 [patent_doc_number] => 11068265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Sequence alignment method of vector processor [patent_app_type] => utility [patent_app_number] => 16/447041 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11673 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447041 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447041
Sequence alignment method of vector processor Jun 19, 2019 Issued
Array ( [id] => 17861572 [patent_doc_number] => 11442728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Sequence alignment method of vector processor [patent_app_type] => utility [patent_app_number] => 16/447035 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11644 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447035 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447035
Sequence alignment method of vector processor Jun 19, 2019 Issued
Array ( [id] => 16514782 [patent_doc_number] => 20200394040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => LIMITING REPLAY OF LOAD-BASED CONTROL INDEPENDENT (CI) INSTRUCTIONS IN SPECULATIVE MISPREDICTION RECOVERY IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/440062 [patent_app_country] => US [patent_app_date] => 2019-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16440062 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/440062
Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processor Jun 12, 2019 Issued
Array ( [id] => 16514782 [patent_doc_number] => 20200394040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => LIMITING REPLAY OF LOAD-BASED CONTROL INDEPENDENT (CI) INSTRUCTIONS IN SPECULATIVE MISPREDICTION RECOVERY IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/440062 [patent_app_country] => US [patent_app_date] => 2019-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16440062 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/440062
Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processor Jun 12, 2019 Issued
Array ( [id] => 14629231 [patent_doc_number] => 20190227983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => EXECUTION ENGINE FOR EXECUTING SINGLE ASSIGNMENT PROGRAMS WITH AFFINE DEPENDENCIES [patent_app_type] => utility [patent_app_number] => 16/372069 [patent_app_country] => US [patent_app_date] => 2019-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16372069 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/372069
Execution engine for executing single assignment programs with affine dependencies Mar 31, 2019 Issued
Array ( [id] => 16864492 [patent_doc_number] => 11023232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Control transfer termination instructions of an instruction set architecture (ISA) [patent_app_type] => utility [patent_app_number] => 16/352051 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9440 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352051 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/352051
Control transfer termination instructions of an instruction set architecture (ISA) Mar 12, 2019 Issued
Array ( [id] => 14935761 [patent_doc_number] => 20190303518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => SYSTEMS AND METHODS FOR IMPLEMENTING A MACHINE PERCEPTION AND DENSE ALGORITHM INTEGRATED CIRCUIT AND ENABLING A FLOWING PROPAGATION OF DATA WITHIN THE INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/292537 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292537 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292537
Systems and methods for implementing a machine perception and dense algorithm integrated circuit and enabling a flowing propagation of data within the integrated circuit Mar 4, 2019 Issued
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