Search

William B. Partridge

Examiner (ID: 2252, Phone: (571)270-1402 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2812
Total Applications
515
Issued Applications
410
Pending Applications
5
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5565829 [patent_doc_number] => 20090138682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'Dynamic instruction execution based on transaction priority tagging' [patent_app_type] => utility [patent_app_number] => 11/946504 [patent_app_country] => US [patent_app_date] => 2007-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20090138682.pdf [firstpage_image] =>[orig_patent_app_number] => 11946504 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/946504
Dynamic instruction execution based on transaction priority tagging Nov 27, 2007 Issued
Array ( [id] => 10582651 [patent_doc_number] => 09304775 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-05 [patent_title] => 'Dispatching of instructions for execution by heterogeneous processing engines' [patent_app_type] => utility [patent_app_number] => 11/935266 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7791 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11935266 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935266
Dispatching of instructions for execution by heterogeneous processing engines Nov 4, 2007 Issued
Array ( [id] => 4469930 [patent_doc_number] => 07882333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Architectural enhancements to CPU microcode load mechanism using inter processor interrupt messages' [patent_app_type] => utility [patent_app_number] => 11/934821 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2283 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882333.pdf [firstpage_image] =>[orig_patent_app_number] => 11934821 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934821
Architectural enhancements to CPU microcode load mechanism using inter processor interrupt messages Nov 4, 2007 Issued
Array ( [id] => 4653326 [patent_doc_number] => 20080040583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Digital Data Processing Apparatus Having Asymmetric Hardware Multithreading Support for Different Threads' [patent_app_type] => utility [patent_app_number] => 11/923455 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11648 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040583.pdf [firstpage_image] =>[orig_patent_app_number] => 11923455 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/923455
Digital data processing apparatus having hardware multithreading support including cache line limiting mechanism for special class threads Oct 23, 2007 Issued
Array ( [id] => 8010829 [patent_doc_number] => 08086832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Structure for dynamically adjusting pipelined data paths for improved power management' [patent_app_type] => utility [patent_app_number] => 11/869216 [patent_app_country] => US [patent_app_date] => 2007-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3115 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086832.pdf [firstpage_image] =>[orig_patent_app_number] => 11869216 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/869216
Structure for dynamically adjusting pipelined data paths for improved power management Oct 8, 2007 Issued
Array ( [id] => 5232402 [patent_doc_number] => 20070294511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Programmable Processor Architecture' [patent_app_type] => utility [patent_app_number] => 11/848023 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 13542 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20070294511.pdf [firstpage_image] =>[orig_patent_app_number] => 11848023 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/848023
Programmable Processor Architecture Aug 29, 2007 Abandoned
Array ( [id] => 8120093 [patent_doc_number] => 08161271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Store misaligned vector with permute' [patent_app_type] => utility [patent_app_number] => 11/775999 [patent_app_country] => US [patent_app_date] => 2007-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 14988 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161271.pdf [firstpage_image] =>[orig_patent_app_number] => 11775999 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775999
Store misaligned vector with permute Jul 10, 2007 Issued
Array ( [id] => 5376066 [patent_doc_number] => 20090313627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'TECHNIQUE FOR PERFORMING A SYSTEM SHUTDOWN' [patent_app_type] => utility [patent_app_number] => 12/307327 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6120 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20090313627.pdf [firstpage_image] =>[orig_patent_app_number] => 12307327 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/307327
TECHNIQUE FOR PERFORMING A SYSTEM SHUTDOWN Jun 24, 2007 Abandoned
Array ( [id] => 9416834 [patent_doc_number] => 08700886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Processor configured for operation with multiple operation codes per instruction' [patent_app_type] => utility [patent_app_number] => 11/755511 [patent_app_country] => US [patent_app_date] => 2007-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11755511 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/755511
Processor configured for operation with multiple operation codes per instruction May 29, 2007 Issued
Array ( [id] => 4508166 [patent_doc_number] => 07958333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected' [patent_app_type] => utility [patent_app_number] => 11/755119 [patent_app_country] => US [patent_app_date] => 2007-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11487 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958333.pdf [firstpage_image] =>[orig_patent_app_number] => 11755119 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/755119
Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected May 29, 2007 Issued
Array ( [id] => 6593729 [patent_doc_number] => 20100274997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'Executing a Gather Operation on a Parallel Computer' [patent_app_type] => utility [patent_app_number] => 11/754740 [patent_app_country] => US [patent_app_date] => 2007-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0274/20100274997.pdf [firstpage_image] =>[orig_patent_app_number] => 11754740 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/754740
Executing a gather operation on a parallel computer May 28, 2007 Issued
Array ( [id] => 4934766 [patent_doc_number] => 20080005541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'INFORMATION-PROCESSING APPARATUS AND ACTIVATION METHOD AND PROGRAM THEREOF' [patent_app_type] => utility [patent_app_number] => 11/753100 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10812 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20080005541.pdf [firstpage_image] =>[orig_patent_app_number] => 11753100 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/753100
Information-processing apparatus and activation method and program for activating an operating system in a short period of time May 23, 2007 Issued
Array ( [id] => 8273103 [patent_doc_number] => 08214624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Processing long-latency instructions in a pipelined processor' [patent_app_type] => utility [patent_app_number] => 11/805364 [patent_app_country] => US [patent_app_date] => 2007-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7660 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11805364 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/805364
Processing long-latency instructions in a pipelined processor May 22, 2007 Issued
Array ( [id] => 5387441 [patent_doc_number] => 20090228686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'Energy efficient processing device' [patent_app_type] => utility [patent_app_number] => 11/805510 [patent_app_country] => US [patent_app_date] => 2007-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20090228686.pdf [firstpage_image] =>[orig_patent_app_number] => 11805510 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/805510
Energy efficient processing device May 21, 2007 Abandoned
Array ( [id] => 4469940 [patent_doc_number] => 07882337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Method and system for efficient tentative tracing of software in multiprocessors' [patent_app_type] => utility [patent_app_number] => 11/751007 [patent_app_country] => US [patent_app_date] => 2007-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4562 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882337.pdf [firstpage_image] =>[orig_patent_app_number] => 11751007 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/751007
Method and system for efficient tentative tracing of software in multiprocessors May 18, 2007 Issued
Array ( [id] => 5064826 [patent_doc_number] => 20070226468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Arrangements for controlling instruction and data flow in a multi-processor environment' [patent_app_type] => utility [patent_app_number] => 11/804451 [patent_app_country] => US [patent_app_date] => 2007-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226468.pdf [firstpage_image] =>[orig_patent_app_number] => 11804451 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/804451
Arrangements for controlling instruction and data flow in a multi-processor environment May 17, 2007 Abandoned
Array ( [id] => 4917600 [patent_doc_number] => 20080098201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'PARALLEL DATA PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/750951 [patent_app_country] => US [patent_app_date] => 2007-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12767 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20080098201.pdf [firstpage_image] =>[orig_patent_app_number] => 11750951 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/750951
Thread manager to control an array of processing elements May 17, 2007 Issued
Array ( [id] => 5114985 [patent_doc_number] => 20070198901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'CONFIGURABLE INTERFACE FOR CONNECTING VARIOUS CHIPSETS FOR WIRELESS COMMUNICATION TO A PROGRAMMABLE (MULTI-)PROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/733707 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 17430 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20070198901.pdf [firstpage_image] =>[orig_patent_app_number] => 11733707 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/733707
CONFIGURABLE INTERFACE FOR CONNECTING VARIOUS CHIPSETS FOR WIRELESS COMMUNICATION TO A PROGRAMMABLE (MULTI-)PROCESSOR Apr 9, 2007 Abandoned
Array ( [id] => 47718 [patent_doc_number] => 07783864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Vertical and horizontal pipelining in a system for performing modular multiplication' [patent_app_type] => utility [patent_app_number] => 11/673752 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 14516 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/783/07783864.pdf [firstpage_image] =>[orig_patent_app_number] => 11673752 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673752
Vertical and horizontal pipelining in a system for performing modular multiplication Feb 11, 2007 Issued
Array ( [id] => 4956496 [patent_doc_number] => 20080189520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'USING PERFORMANCE DATA FOR INSTRUCTION THREAD DIRECTION' [patent_app_type] => utility [patent_app_number] => 11/671627 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6320 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20080189520.pdf [firstpage_image] =>[orig_patent_app_number] => 11671627 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/671627
Using performance data for instruction thread direction Feb 5, 2007 Issued
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