
William B. Partridge
Examiner (ID: 2252, Phone: (571)270-1402 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183, 2812 |
| Total Applications | 515 |
| Issued Applications | 410 |
| Pending Applications | 5 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5565829
[patent_doc_number] => 20090138682
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-28
[patent_title] => 'Dynamic instruction execution based on transaction priority tagging'
[patent_app_type] => utility
[patent_app_number] => 11/946504
[patent_app_country] => US
[patent_app_date] => 2007-11-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/946504 | Dynamic instruction execution based on transaction priority tagging | Nov 27, 2007 | Issued |
Array
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[patent_issue_date] => 2016-04-05
[patent_title] => 'Dispatching of instructions for execution by heterogeneous processing engines'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/935266 | Dispatching of instructions for execution by heterogeneous processing engines | Nov 4, 2007 | Issued |
Array
(
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[patent_issue_date] => 2011-02-01
[patent_title] => 'Architectural enhancements to CPU microcode load mechanism using inter processor interrupt messages'
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[patent_app_number] => 11/934821
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[patent_app_date] => 2007-11-05
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/934821 | Architectural enhancements to CPU microcode load mechanism using inter processor interrupt messages | Nov 4, 2007 | Issued |
Array
(
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[patent_doc_number] => 20080040583
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-14
[patent_title] => 'Digital Data Processing Apparatus Having Asymmetric Hardware Multithreading Support for Different Threads'
[patent_app_type] => utility
[patent_app_number] => 11/923455
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/923455 | Digital data processing apparatus having hardware multithreading support including cache line limiting mechanism for special class threads | Oct 23, 2007 | Issued |
Array
(
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[patent_issue_date] => 2011-12-27
[patent_title] => 'Structure for dynamically adjusting pipelined data paths for improved power management'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/869216 | Structure for dynamically adjusting pipelined data paths for improved power management | Oct 8, 2007 | Issued |
Array
(
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[patent_doc_number] => 20070294511
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[patent_issue_date] => 2007-12-20
[patent_title] => 'Programmable Processor Architecture'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/848023 | Programmable Processor Architecture | Aug 29, 2007 | Abandoned |
Array
(
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[patent_title] => 'Store misaligned vector with permute'
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[firstpage_image] =>[orig_patent_app_number] => 11775999
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/775999 | Store misaligned vector with permute | Jul 10, 2007 | Issued |
Array
(
[id] => 5376066
[patent_doc_number] => 20090313627
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[patent_kind] => A1
[patent_issue_date] => 2009-12-17
[patent_title] => 'TECHNIQUE FOR PERFORMING A SYSTEM SHUTDOWN'
[patent_app_type] => utility
[patent_app_number] => 12/307327
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/307327 | TECHNIQUE FOR PERFORMING A SYSTEM SHUTDOWN | Jun 24, 2007 | Abandoned |
Array
(
[id] => 9416834
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[patent_issue_date] => 2014-04-15
[patent_title] => 'Processor configured for operation with multiple operation codes per instruction'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/755511 | Processor configured for operation with multiple operation codes per instruction | May 29, 2007 | Issued |
Array
(
[id] => 4508166
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[patent_issue_date] => 2011-06-07
[patent_title] => 'Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected'
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[patent_app_number] => 11/755119
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Array
(
[id] => 6593729
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[patent_title] => 'Executing a Gather Operation on a Parallel Computer'
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Array
(
[id] => 4934766
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/753100 | Information-processing apparatus and activation method and program for activating an operating system in a short period of time | May 23, 2007 | Issued |
Array
(
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/751007 | Method and system for efficient tentative tracing of software in multiprocessors | May 18, 2007 | Issued |
Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/671627 | Using performance data for instruction thread direction | Feb 5, 2007 | Issued |