Search

William B. Partridge

Examiner (ID: 11002, Phone: (571)270-1402 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2812, 2183
Total Applications
515
Issued Applications
410
Pending Applications
5
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5891907 [patent_doc_number] => 20060277395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'Processor performance monitoring' [patent_app_type] => utility [patent_app_number] => 11/145601 [patent_app_country] => US [patent_app_date] => 2005-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7253 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20060277395.pdf [firstpage_image] =>[orig_patent_app_number] => 11145601 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/145601
Processor performance monitoring Jun 5, 2005 Abandoned
Array ( [id] => 5610254 [patent_doc_number] => 20060271770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Branch prediction control' [patent_app_type] => utility [patent_app_number] => 11/139984 [patent_app_country] => US [patent_app_date] => 2005-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3227 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20060271770.pdf [firstpage_image] =>[orig_patent_app_number] => 11139984 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/139984
Branch prediction apparatus for repurposing a branch to instruction set as a non-predicted branch May 30, 2005 Issued
Array ( [id] => 58116 [patent_doc_number] => 07774582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Result bypassing to override a data hazard within a superscalar processor' [patent_app_type] => utility [patent_app_number] => 11/137792 [patent_app_country] => US [patent_app_date] => 2005-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3959 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/774/07774582.pdf [firstpage_image] =>[orig_patent_app_number] => 11137792 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/137792
Result bypassing to override a data hazard within a superscalar processor May 25, 2005 Issued
Array ( [id] => 8355006 [patent_doc_number] => 08250348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Methods and apparatus for dynamically switching processor mode' [patent_app_type] => utility [patent_app_number] => 11/132658 [patent_app_country] => US [patent_app_date] => 2005-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11950 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11132658 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/132658
Methods and apparatus for dynamically switching processor mode May 18, 2005 Issued
Array ( [id] => 5734628 [patent_doc_number] => 20060259745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Processor having efficient function estimate instructions' [patent_app_type] => utility [patent_app_number] => 11/127848 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259745.pdf [firstpage_image] =>[orig_patent_app_number] => 11127848 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/127848
Processor having efficient function estimate instructions May 11, 2005 Issued
Array ( [id] => 5822085 [patent_doc_number] => 20060026398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Unpack instruction' [patent_app_type] => utility [patent_app_number] => 11/116918 [patent_app_country] => US [patent_app_date] => 2005-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4669 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026398.pdf [firstpage_image] =>[orig_patent_app_number] => 11116918 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/116918
Unpack instruction Apr 27, 2005 Abandoned
Array ( [id] => 5822084 [patent_doc_number] => 20060026397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Pack instruction' [patent_app_type] => utility [patent_app_number] => 11/116897 [patent_app_country] => US [patent_app_date] => 2005-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4552 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026397.pdf [firstpage_image] =>[orig_patent_app_number] => 11116897 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/116897
Pack instruction Apr 27, 2005 Abandoned
Array ( [id] => 5822083 [patent_doc_number] => 20060026396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Memory access instruction with optional error check' [patent_app_type] => utility [patent_app_number] => 11/116893 [patent_app_country] => US [patent_app_date] => 2005-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4552 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026396.pdf [firstpage_image] =>[orig_patent_app_number] => 11116893 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/116893
Memory access instruction with optional error check Apr 27, 2005 Abandoned
Array ( [id] => 5927919 [patent_doc_number] => 20060242390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Advanced load address table buffer' [patent_app_type] => utility [patent_app_number] => 11/114754 [patent_app_country] => US [patent_app_date] => 2005-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5216 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20060242390.pdf [firstpage_image] =>[orig_patent_app_number] => 11114754 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/114754
Advanced load address table buffer Apr 25, 2005 Abandoned
Array ( [id] => 6962543 [patent_doc_number] => 20050216779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Device and method for managing a standby state of microprocessor' [patent_app_type] => utility [patent_app_number] => 11/083350 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5188 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216779.pdf [firstpage_image] =>[orig_patent_app_number] => 11083350 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/083350
Device and method for managing a standby state of microprocessor Mar 15, 2005 Abandoned
Array ( [id] => 5143979 [patent_doc_number] => 20070006195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Method and structure for explicit software control of data speculation' [patent_app_type] => utility [patent_app_number] => 11/082281 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5877 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20070006195.pdf [firstpage_image] =>[orig_patent_app_number] => 11082281 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/082281
Method and structure for explicit software control of data speculation Mar 15, 2005 Abandoned
Array ( [id] => 245086 [patent_doc_number] => 07590830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Method and structure for concurrent branch prediction in a processor' [patent_app_type] => utility [patent_app_number] => 11/068626 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4844 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590830.pdf [firstpage_image] =>[orig_patent_app_number] => 11068626 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/068626
Method and structure for concurrent branch prediction in a processor Feb 27, 2005 Issued
Array ( [id] => 7006790 [patent_doc_number] => 20050172103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Array-type computer processor' [patent_app_type] => utility [patent_app_number] => 11/049305 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172103.pdf [firstpage_image] =>[orig_patent_app_number] => 11049305 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/049305
Array—type computer processor with reduced instruction storage Feb 2, 2005 Issued
Array ( [id] => 1078869 [patent_doc_number] => 07617389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Event notifying method, event notifying device and processor system permitting inconsistent state of a counter managing number of non-notified events' [patent_app_type] => utility [patent_app_number] => 11/032193 [patent_app_country] => US [patent_app_date] => 2005-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7321 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/617/07617389.pdf [firstpage_image] =>[orig_patent_app_number] => 11032193 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/032193
Event notifying method, event notifying device and processor system permitting inconsistent state of a counter managing number of non-notified events Jan 10, 2005 Issued
Array ( [id] => 5695808 [patent_doc_number] => 20060155955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'SIMD-RISC processor module' [patent_app_type] => utility [patent_app_number] => 11/032194 [patent_app_country] => US [patent_app_date] => 2005-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 12911 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20060155955.pdf [firstpage_image] =>[orig_patent_app_number] => 11032194 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/032194
SIMD-RISC processor module Jan 9, 2005 Abandoned
Array ( [id] => 5695814 [patent_doc_number] => 20060155961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processor' [patent_app_type] => utility [patent_app_number] => 11/030339 [patent_app_country] => US [patent_app_date] => 2005-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2830 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20060155961.pdf [firstpage_image] =>[orig_patent_app_number] => 11030339 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/030339
Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processor Jan 5, 2005 Abandoned
Array ( [id] => 5809388 [patent_doc_number] => 20060095744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Memory control circuit and microprocessor system' [patent_app_type] => utility [patent_app_number] => 11/024843 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7643 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095744.pdf [firstpage_image] =>[orig_patent_app_number] => 11024843 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024843
Memory control circuit and microprocessory system for pre-fetching instructions Dec 29, 2004 Issued
Array ( [id] => 5633451 [patent_doc_number] => 20060149922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Multiple computational clusters in processors and methods thereof' [patent_app_type] => utility [patent_app_number] => 11/022822 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9336 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20060149922.pdf [firstpage_image] =>[orig_patent_app_number] => 11022822 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/022822
Multiple computational clusters in processors and methods thereof Dec 27, 2004 Abandoned
Array ( [id] => 5822156 [patent_doc_number] => 20060026469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Branch prediction device, control method thereof and information processing device' [patent_app_type] => utility [patent_app_number] => 10/994411 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026469.pdf [firstpage_image] =>[orig_patent_app_number] => 10994411 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/994411
Branch prediction device, control method thereof and information processing device Nov 22, 2004 Abandoned
Array ( [id] => 4572566 [patent_doc_number] => 07962716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements' [patent_app_type] => utility [patent_app_number] => 10/990800 [patent_app_country] => US [patent_app_date] => 2004-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8509 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962716.pdf [firstpage_image] =>[orig_patent_app_number] => 10990800 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/990800
Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements Nov 16, 2004 Issued
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