Search

William B. Partridge

Examiner (ID: 7131, Phone: (571)270-1402 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2812, 2183
Total Applications
514
Issued Applications
410
Pending Applications
4
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17269155 [patent_doc_number] => 11194580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Selective suppression of instruction translation lookaside buffer (ITLB) access [patent_app_type] => utility [patent_app_number] => 16/286819 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 10129 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286819 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/286819
Selective suppression of instruction translation lookaside buffer (ITLB) access Feb 26, 2019 Issued
Array ( [id] => 14506361 [patent_doc_number] => 20190196835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => SELECTIVE SUPPRESSION OF INSTRUCTION CACHE-RELATED DIRECTORY ACCESS [patent_app_type] => utility [patent_app_number] => 16/286809 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/286809
Selective suppression of instruction cache-related directory access Feb 26, 2019 Issued
Array ( [id] => 14506361 [patent_doc_number] => 20190196835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => SELECTIVE SUPPRESSION OF INSTRUCTION CACHE-RELATED DIRECTORY ACCESS [patent_app_type] => utility [patent_app_number] => 16/286809 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/286809
Selective suppression of instruction cache-related directory access Feb 26, 2019 Issued
Array ( [id] => 16833909 [patent_doc_number] => 11010160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Load register on condition immediate instruction [patent_app_type] => utility [patent_app_number] => 16/281976 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281976 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281976
Load register on condition immediate instruction Feb 20, 2019 Issued
Array ( [id] => 16787972 [patent_doc_number] => 10990405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Call/return stack branch target predictor to multiple next sequential instruction addresses [patent_app_type] => utility [patent_app_number] => 16/279250 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16279250 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/279250
Call/return stack branch target predictor to multiple next sequential instruction addresses Feb 18, 2019 Issued
Array ( [id] => 16255512 [patent_doc_number] => 20200264886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => REDUCTION OF INTERRUPT SERVICE LATENCY IN MULTI-PROCESSOR SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/279103 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16279103 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/279103
Reduction of interrupt service latency in multi-processor systems Feb 18, 2019 Issued
Array ( [id] => 17106212 [patent_doc_number] => 11126429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Apparatus and methods for bitwise vector operations [patent_app_type] => utility [patent_app_number] => 16/250148 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4974 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16250148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/250148
Apparatus and methods for bitwise vector operations Jan 16, 2019 Issued
Array ( [id] => 14281895 [patent_doc_number] => 20190138232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => LOCAL INSTRUCTION ORDERING BASED ON MEMORY DOMAINS [patent_app_type] => utility [patent_app_number] => 16/240104 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16240104 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/240104
Local instruction ordering based on memory domains Jan 3, 2019 Issued
Array ( [id] => 14411237 [patent_doc_number] => 20190171462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => PROCESSING CORE HAVING SHARED FRONT END UNIT [patent_app_type] => utility [patent_app_number] => 16/200203 [patent_app_country] => US [patent_app_date] => 2018-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16200203 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/200203
PROCESSING CORE HAVING SHARED FRONT END UNIT Nov 25, 2018 Abandoned
Array ( [id] => 14135563 [patent_doc_number] => 20190102171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 16/194668 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194668 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194668
Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture Nov 18, 2018 Issued
Array ( [id] => 17339645 [patent_doc_number] => 20220005976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => MICRO LED DEVICE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/293436 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17293436 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/293436
MICRO LED DEVICE AND METHOD FOR MANUFACTURING SAME Nov 15, 2018 Abandoned
Array ( [id] => 14022451 [patent_doc_number] => 20190073219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => APPARATUS AND METHODS FOR VECTOR OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/171987 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171987 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/171987
APPARATUS AND METHODS FOR VECTOR OPERATIONS Oct 25, 2018 Abandoned
Array ( [id] => 13875727 [patent_doc_number] => 20190034204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => REDUCING DATA HAZARDS IN PIPELINED PROCESSORS TO PROVIDE HIGH PROCESSOR UTILIZATION [patent_app_type] => utility [patent_app_number] => 16/150527 [patent_app_country] => US [patent_app_date] => 2018-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16150527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/150527
Reducing data hazards in pipelined processors to provide high processor utilization Oct 2, 2018 Issued
Array ( [id] => 14047325 [patent_doc_number] => 20190079769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/130856 [patent_app_country] => US [patent_app_date] => 2018-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34522 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16130856 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/130856
PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A PROCESSOR Sep 12, 2018 Abandoned
Array ( [id] => 14009313 [patent_doc_number] => 10223115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Data read-write scheduler and reservation station for vector operations [patent_app_type] => utility [patent_app_number] => 16/039605 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8047 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039605 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/039605
Data read-write scheduler and reservation station for vector operations Jul 18, 2018 Issued
Array ( [id] => 13626927 [patent_doc_number] => 20180365015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => BYTECODE PROCESSING DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/006962 [patent_app_country] => US [patent_app_date] => 2018-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16006962 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/006962
Bytecode processing device and operation method thereof Jun 12, 2018 Issued
Array ( [id] => 17180039 [patent_doc_number] => 11157281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Prefetching data based on register-activity patterns [patent_app_type] => utility [patent_app_number] => 15/988070 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4477 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15988070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/988070
Prefetching data based on register-activity patterns May 23, 2018 Issued
Array ( [id] => 17180039 [patent_doc_number] => 11157281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Prefetching data based on register-activity patterns [patent_app_type] => utility [patent_app_number] => 15/988070 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4477 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15988070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/988070
Prefetching data based on register-activity patterns May 23, 2018 Issued
Array ( [id] => 15486225 [patent_doc_number] => 10558462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Apparatus and method for storing source operands for operations [patent_app_type] => utility [patent_app_number] => 15/987002 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9238 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987002 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987002
Apparatus and method for storing source operands for operations May 22, 2018 Issued
Array ( [id] => 15136891 [patent_doc_number] => 10481913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Token-based data dependency protection for memory access [patent_app_type] => utility [patent_app_number] => 15/967619 [patent_app_country] => US [patent_app_date] => 2018-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967619 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967619
Token-based data dependency protection for memory access Apr 30, 2018 Issued
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