
William B. Partridge
Examiner (ID: 9488, Phone: (571)270-1402 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2812, 2183 |
| Total Applications | 515 |
| Issued Applications | 410 |
| Pending Applications | 5 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1345938
[patent_doc_number] => 06582991
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-24
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => B1
[patent_app_number] => 09/886997
[patent_app_country] => US
[patent_app_date] => 2001-06-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/582/06582991.pdf
[firstpage_image] =>[orig_patent_app_number] => 09886997
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/886997 | Semiconductor device and method for fabricating the same | Jun 24, 2001 | Issued |
Array
(
[id] => 1347252
[patent_doc_number] => 06579773
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-06-17
[patent_title] => 'Transistor device and fabrication method thereof'
[patent_app_type] => B2
[patent_app_number] => 09/887037
[patent_app_country] => US
[patent_app_date] => 2001-06-25
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[firstpage_image] =>[orig_patent_app_number] => 09887037
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/887037 | Transistor device and fabrication method thereof | Jun 24, 2001 | Issued |
Array
(
[id] => 6327625
[patent_doc_number] => 20020197882
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-26
[patent_title] => 'TEMPERATURE SPIKE FOR UNIFORM NITRIDIZATION OF ULTRA-THIN SILICON DIOXIDE LAYERS IN TRANSISTOR GATES'
[patent_app_type] => new
[patent_app_number] => 09/885587
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[pdf_file] => publications/A1/0197/20020197882.pdf
[firstpage_image] =>[orig_patent_app_number] => 09885587
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/885587 | Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates | Jun 19, 2001 | Issued |
Array
(
[id] => 7634784
[patent_doc_number] => 06656834
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-02
[patent_title] => 'Method of selectively alloying interconnect regions by deposition process'
[patent_app_type] => B1
[patent_app_number] => 09/884027
[patent_app_country] => US
[patent_app_date] => 2001-06-20
[patent_effective_date] => 0000-00-00
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Array
(
[id] => 7645703
[patent_doc_number] => 06472266
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-29
[patent_title] => 'Method to reduce bit line capacitance in cub drams'
[patent_app_type] => B1
[patent_app_number] => 09/882427
[patent_app_country] => US
[patent_app_date] => 2001-06-18
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09882427
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/882427 | Method to reduce bit line capacitance in cub drams | Jun 17, 2001 | Issued |
Array
(
[id] => 6884944
[patent_doc_number] => 20010039106
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[patent_issue_date] => 2001-11-08
[patent_title] => 'Process for producing an integrated semiconductor memory configuration'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/883011 | Process for producing an integrated semiconductor memory configuration | Jun 14, 2001 | Issued |
Array
(
[id] => 1380186
[patent_doc_number] => 06563192
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[patent_issue_date] => 2003-05-13
[patent_title] => 'Semiconductor die with integral decoupling capacitor'
[patent_app_type] => B1
[patent_app_number] => 09/882469
[patent_app_country] => US
[patent_app_date] => 2001-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/563/06563192.pdf
[firstpage_image] =>[orig_patent_app_number] => 09882469
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/882469 | Semiconductor die with integral decoupling capacitor | Jun 13, 2001 | Issued |
Array
(
[id] => 1503330
[patent_doc_number] => 06465276
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-10-15
[patent_title] => 'Power semiconductor package and method for making the same'
[patent_app_type] => B2
[patent_app_number] => 09/879367
[patent_app_country] => US
[patent_app_date] => 2001-06-12
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09879367
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/879367 | Power semiconductor package and method for making the same | Jun 11, 2001 | Issued |
Array
(
[id] => 1354062
[patent_doc_number] => 06576488
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-06-10
[patent_title] => 'Using electrophoresis to produce a conformally coated phosphor-converted light emitting semiconductor'
[patent_app_type] => B2
[patent_app_number] => 09/879627
[patent_app_country] => US
[patent_app_date] => 2001-06-11
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[firstpage_image] =>[orig_patent_app_number] => 09879627
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/879627 | Using electrophoresis to produce a conformally coated phosphor-converted light emitting semiconductor | Jun 10, 2001 | Issued |
Array
(
[id] => 7000635
[patent_doc_number] => 20010053592
[patent_country] => US
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[patent_issue_date] => 2001-12-20
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => new
[patent_app_number] => 09/876207
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 09876207
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/876207 | Method of manufacturing semiconductor device | Jun 5, 2001 | Issued |
Array
(
[id] => 1581238
[patent_doc_number] => 06423637
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-23
[patent_title] => 'Method of manufacturing copper wiring in a semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/875687
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[pdf_file] => patents/06/423/06423637.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/875687 | Method of manufacturing copper wiring in a semiconductor device | Jun 5, 2001 | Issued |
Array
(
[id] => 6408435
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[patent_title] => 'Flexible package fabrication method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/865417 | Flexible package fabrication method | May 28, 2001 | Abandoned |
Array
(
[id] => 1155339
[patent_doc_number] => 06764875
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[patent_title] => 'Method of and apparatus for sealing an hermetic lid to a semiconductor die'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/866266 | Method of and apparatus for sealing an hermetic lid to a semiconductor die | May 23, 2001 | Issued |
Array
(
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[patent_title] => 'Method and system for detecting metal contamination on a semiconductor wafer'
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Array
(
[id] => 5870665
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/850587 | Electronic component having a semiconductor chip | May 6, 2001 | Issued |
| 09/786387 | Transponder module and a method for producing the same | Apr 30, 2001 | Abandoned |
Array
(
[id] => 1381791
[patent_doc_number] => 06551886
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[patent_title] => 'Ultra-thin body SOI MOSFET and gate-last fabrication method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/844637 | Ultra-thin body SOI MOSFET and gate-last fabrication method | Apr 26, 2001 | Issued |
Array
(
[id] => 1518939
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[patent_title] => 'Topographical electrostatic protection grid for sensors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/843260 | Topographical electrostatic protection grid for sensors | Apr 24, 2001 | Issued |
Array
(
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Array
(
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