Search

William B. Partridge

Examiner (ID: 7131, Phone: (571)270-1402 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2812, 2183
Total Applications
514
Issued Applications
410
Pending Applications
4
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14966771 [patent_doc_number] => 20190310864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => Selecting a Precision Level for Executing a Workload in an Electronic Device [patent_app_type] => utility [patent_app_number] => 15/948795 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948795 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/948795
Selecting a precision level for executing a workload in an electronic device Apr 8, 2018 Issued
Array ( [id] => 13497203 [patent_doc_number] => 20180300144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => CONTROL SYSTEM AND METHOD OF MEMORY ACCESS [patent_app_type] => utility [patent_app_number] => 15/945114 [patent_app_country] => US [patent_app_date] => 2018-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15945114 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/945114
Control system for process data and method for controlling process data Apr 3, 2018 Issued
Array ( [id] => 13540787 [patent_doc_number] => 20180321940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS [patent_app_type] => utility [patent_app_number] => 15/939693 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15939693 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/939693
Rotate instructions that complete execution either without writing or reading flags Mar 28, 2018 Issued
Array ( [id] => 15313063 [patent_doc_number] => 10521236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Branch prediction based on coherence operations in processors [patent_app_type] => utility [patent_app_number] => 15/940408 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 42 [patent_no_of_words] => 28805 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15940408 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/940408
Branch prediction based on coherence operations in processors Mar 28, 2018 Issued
Array ( [id] => 14506597 [patent_doc_number] => 20190196953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => MEMORY LOOKUP COMPUTING MECHANISMS [patent_app_type] => utility [patent_app_number] => 15/913758 [patent_app_country] => US [patent_app_date] => 2018-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15913758 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/913758
Computing mechanisms using lookup tables stored on memory Mar 5, 2018 Issued
Array ( [id] => 15231587 [patent_doc_number] => 10503515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Methods and apparatus for adjacency network delivery of operands to instruction specified destinations that reduces storage of temporary variables [patent_app_type] => utility [patent_app_number] => 15/910211 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 59 [patent_no_of_words] => 30828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910211 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910211
Methods and apparatus for adjacency network delivery of operands to instruction specified destinations that reduces storage of temporary variables Mar 1, 2018 Issued
Array ( [id] => 15012511 [patent_doc_number] => 10452400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Multi-thread processor with multi-bank branch-target buffer [patent_app_type] => utility [patent_app_number] => 15/904474 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4952 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904474 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/904474
Multi-thread processor with multi-bank branch-target buffer Feb 25, 2018 Issued
Array ( [id] => 15313067 [patent_doc_number] => 10521238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Apparatus, systems, and methods for low power computational imaging [patent_app_type] => utility [patent_app_number] => 15/900368 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 19329 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900368 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900368
Apparatus, systems, and methods for low power computational imaging Feb 19, 2018 Issued
Array ( [id] => 14689305 [patent_doc_number] => 20190243768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => MEMORY WRITE LOG STORAGE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 15/891028 [patent_app_country] => US [patent_app_date] => 2018-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15891028 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/891028
Memory write log storage processors, methods, systems, and instructions Feb 6, 2018 Issued
Array ( [id] => 16927080 [patent_doc_number] => 11048563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Synchronization with a host processor [patent_app_type] => utility [patent_app_number] => 15/886065 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 28780 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15886065 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/886065
Synchronization with a host processor Jan 31, 2018 Issued
Array ( [id] => 15012503 [patent_doc_number] => 10452396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Combining states of multiple threads in a multi-threaded processor [patent_app_type] => utility [patent_app_number] => 15/885955 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 18205 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885955 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/885955
Combining states of multiple threads in a multi-threaded processor Jan 31, 2018 Issued
Array ( [id] => 15059141 [patent_doc_number] => 10459876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Performing concurrent operations in a processing element [patent_app_type] => utility [patent_app_number] => 15/885592 [patent_app_country] => US [patent_app_date] => 2018-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 14322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885592 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/885592
Performing concurrent operations in a processing element Jan 30, 2018 Issued
Array ( [id] => 14886773 [patent_doc_number] => 10423429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Reconfiguring processing groups for cascading data workloads [patent_app_type] => utility [patent_app_number] => 15/860010 [patent_app_country] => US [patent_app_date] => 2018-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15860010 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/860010
Reconfiguring processing groups for cascading data workloads Jan 1, 2018 Issued
Array ( [id] => 14825187 [patent_doc_number] => 10409601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Apparatus and method for loop flattening and reduction in a single instruction multiple data (SIMD) pipeline [patent_app_type] => utility [patent_app_number] => 15/859046 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 15608 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859046 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859046
Apparatus and method for loop flattening and reduction in a single instruction multiple data (SIMD) pipeline Dec 28, 2017 Issued
Array ( [id] => 18414784 [patent_doc_number] => 11669326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Systems, methods, and apparatuses for dot product operations [patent_app_type] => utility [patent_app_number] => 15/859271 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 42 [patent_no_of_words] => 20227 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859271 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859271
Systems, methods, and apparatuses for dot product operations Dec 28, 2017 Issued
Array ( [id] => 14539031 [patent_doc_number] => 20190205137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => METHODS AND APPARATUS FOR MULTI-LOAD AND MULTI-STORE VECTOR INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 15/859033 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859033 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859033
METHODS AND APPARATUS FOR MULTI-LOAD AND MULTI-STORE VECTOR INSTRUCTIONS Dec 28, 2017 Abandoned
Array ( [id] => 12647391 [patent_doc_number] => 20180107628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => Computer Subsystem and Computer System with Composite Nodes in an Interconnection Structure [patent_app_type] => utility [patent_app_number] => 15/845450 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845450 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845450
Computer subsystem and computer system with composite nodes in an interconnection structure Dec 17, 2017 Issued
Array ( [id] => 17180038 [patent_doc_number] => 11157280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Dynamic fusion based on operand size [patent_app_type] => utility [patent_app_number] => 15/834403 [patent_app_country] => US [patent_app_date] => 2017-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6891 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15834403 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/834403
Dynamic fusion based on operand size Dec 6, 2017 Issued
Array ( [id] => 16446928 [patent_doc_number] => 10838857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Multi-section garbage collection [patent_app_type] => utility [patent_app_number] => 15/832207 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832207 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/832207
Multi-section garbage collection Dec 4, 2017 Issued
Array ( [id] => 16292081 [patent_doc_number] => 10768931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Fine-grained management of exception enablement of floating point controls [patent_app_type] => utility [patent_app_number] => 15/812529 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 38 [patent_no_of_words] => 17545 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15812529 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/812529
Fine-grained management of exception enablement of floating point controls Nov 13, 2017 Issued
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