Search

William B. Partridge

Examiner (ID: 7131, Phone: (571)270-1402 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2812, 2183
Total Applications
514
Issued Applications
410
Pending Applications
4
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15231585 [patent_doc_number] => 10503514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Method for implementing a reduced size register view data structure in a microprocessor [patent_app_type] => utility [patent_app_number] => 15/806189 [patent_app_country] => US [patent_app_date] => 2017-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15806189 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/806189
Method for implementing a reduced size register view data structure in a microprocessor Nov 6, 2017 Issued
Array ( [id] => 13579877 [patent_doc_number] => 20180341487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => SEQUENCE ALIGNMENT METHOD OF VECTOR PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/802844 [patent_app_country] => US [patent_app_date] => 2017-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802844 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/802844
Sequence alignment method of vector processor Nov 2, 2017 Issued
Array ( [id] => 14555415 [patent_doc_number] => 10346169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Selective suppression of instruction cache-related directory access [patent_app_type] => utility [patent_app_number] => 15/793078 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 9999 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15793078 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/793078
Selective suppression of instruction cache-related directory access Oct 24, 2017 Issued
Array ( [id] => 12665731 [patent_doc_number] => 20180113743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => COMMUNICATION ARCHITECTURE FOR EXCHANGING DATA BETWEEN PROCESSING UNITS [patent_app_type] => utility [patent_app_number] => 15/793817 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2838 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15793817 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/793817
Communication architecture for exchanging data between processing units Oct 24, 2017 Issued
Array ( [id] => 14489755 [patent_doc_number] => 10331666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-25 [patent_title] => Apparatus and method for parallel processing of a query [patent_app_type] => utility [patent_app_number] => 15/792227 [patent_app_country] => US [patent_app_date] => 2017-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3506 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792227 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/792227
Apparatus and method for parallel processing of a query Oct 23, 2017 Issued
Array ( [id] => 15919425 [patent_doc_number] => 10656951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Pipeline including separate hardware data paths for different instruction types [patent_app_type] => utility [patent_app_number] => 15/789318 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7432 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15789318 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/789318
Pipeline including separate hardware data paths for different instruction types Oct 19, 2017 Issued
Array ( [id] => 12180563 [patent_doc_number] => 20180039499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'SELECTIVE SUPPRESSION OF INSTRUCTION TRANSLATION LOOKASIDE BUFFER (ITLB) ACCESS' [patent_app_type] => utility [patent_app_number] => 15/785684 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10353 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785684 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785684
Selective suppression of instruction translation lookaside buffer (ITLB) access Oct 16, 2017 Issued
Array ( [id] => 14766333 [patent_doc_number] => 10394562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Microprocessor that fuses if-then instructions [patent_app_type] => utility [patent_app_number] => 15/728551 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 10250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728551 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728551
Microprocessor that fuses if-then instructions Oct 9, 2017 Issued
Array ( [id] => 14149391 [patent_doc_number] => 10255076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Method for performing dual dispatch of blocks and half blocks [patent_app_type] => utility [patent_app_number] => 15/706056 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9578 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706056 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706056
Method for performing dual dispatch of blocks and half blocks Sep 14, 2017 Issued
Array ( [id] => 12094549 [patent_doc_number] => 20170351642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'EXECUTION ENGINE FOR EXECUTING SINGLE ASSIGNMENT PROGRAMS WITH AFFINE DEPENDENCIES' [patent_app_type] => utility [patent_app_number] => 15/683510 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8075 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683510 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/683510
Execution engine for executing single assignment programs with affine dependencies Aug 21, 2017 Issued
Array ( [id] => 12053262 [patent_doc_number] => 20170329605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'APPARATUS AND METHOD OF IMPROVED INSERT INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 15/668508 [patent_app_country] => US [patent_app_date] => 2017-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 23224 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15668508 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/668508
Apparatus and method of improved insert instructions Aug 2, 2017 Issued
Array ( [id] => 18189296 [patent_doc_number] => 11579881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Instructions for vector operations with constant values [patent_app_type] => utility [patent_app_number] => 15/638074 [patent_app_country] => US [patent_app_date] => 2017-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 49 [patent_no_of_words] => 35741 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15638074 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/638074
Instructions for vector operations with constant values Jun 28, 2017 Issued
Array ( [id] => 11989621 [patent_doc_number] => 20170293775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'Control Transfer Termination Instructions Of An Instruction Set Architecture (ISA)' [patent_app_type] => utility [patent_app_number] => 15/635294 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9650 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635294 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/635294
Control transfer termination instructions of an instruction set architecture (ISA) Jun 27, 2017 Issued
Array ( [id] => 14704209 [patent_doc_number] => 10379851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Fine-grained management of exception enablement of floating point controls [patent_app_type] => utility [patent_app_number] => 15/631086 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 38 [patent_no_of_words] => 17869 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631086 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/631086
Fine-grained management of exception enablement of floating point controls Jun 22, 2017 Issued
Array ( [id] => 16232518 [patent_doc_number] => 10740067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Selective updating of floating point controls [patent_app_type] => utility [patent_app_number] => 15/631061 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 38 [patent_no_of_words] => 17919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631061 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/631061
Selective updating of floating point controls Jun 22, 2017 Issued
Array ( [id] => 16385823 [patent_doc_number] => 10810664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Item processing exception configurable pipeline [patent_app_type] => utility [patent_app_number] => 15/627659 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6563 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627659
Item processing exception configurable pipeline Jun 19, 2017 Issued
Array ( [id] => 13974329 [patent_doc_number] => 10216521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Error mitigation for resilient algorithms [patent_app_type] => utility [patent_app_number] => 15/628403 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628403 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628403
Error mitigation for resilient algorithms Jun 19, 2017 Issued
Array ( [id] => 13706805 [patent_doc_number] => 20170364357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => Fetching Instructions in an Instruction Fetch Unit [patent_app_type] => utility [patent_app_number] => 15/624121 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15624121 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/624121
Fetching instructions in an instruction fetch unit Jun 14, 2017 Issued
Array ( [id] => 14704225 [patent_doc_number] => 10379859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Inference based condition code generation [patent_app_type] => utility [patent_app_number] => 15/585234 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5781 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585234 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/585234
Inference based condition code generation May 2, 2017 Issued
Array ( [id] => 14704227 [patent_doc_number] => 10379860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Inference based condition code generation [patent_app_type] => utility [patent_app_number] => 15/585241 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5781 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585241 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/585241
Inference based condition code generation May 2, 2017 Issued
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