Search

William B. Partridge

Examiner (ID: 7131, Phone: (571)270-1402 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2812, 2183
Total Applications
514
Issued Applications
410
Pending Applications
4
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13512815 [patent_doc_number] => 20180307950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => COMPUTE OPTIMIZATIONS FOR NEURAL NETWORKS [patent_app_type] => utility [patent_app_number] => 15/494710 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15494710 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/494710
Compute optimizations for neural networks Apr 23, 2017 Issued
Array ( [id] => 11996177 [patent_doc_number] => 20170300332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'APPARATUS AND METHOD OF IMPROVED INSERT INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 15/476356 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 23223 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15476356 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/476356
Apparatus and method of improved insert instructions Mar 30, 2017 Issued
Array ( [id] => 11716918 [patent_doc_number] => 20170185417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'WORKLOAD OPTIMIZED SERVER FOR INTELLIGENT ALGORITHM TRADING PLATFORMS' [patent_app_type] => utility [patent_app_number] => 15/456457 [patent_app_country] => US [patent_app_date] => 2017-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7611 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15456457 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/456457
Workload optimized server for intelligent algorithm trading platforms Mar 9, 2017 Issued
Array ( [id] => 13891437 [patent_doc_number] => 10198266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Method for populating register view data structure by using register template snapshots [patent_app_type] => utility [patent_app_number] => 15/408269 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9662 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408269 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408269
Method for populating register view data structure by using register template snapshots Jan 16, 2017 Issued
Array ( [id] => 11606504 [patent_doc_number] => 20170123807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'METHOD FOR EMULATING A GUEST CENTRALIZED FLAG ARCHITECTURE BY USING A NATIVE DISTRIBUTED FLAG ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/408323 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 9861 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408323 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408323
METHOD FOR EMULATING A GUEST CENTRALIZED FLAG ARCHITECTURE BY USING A NATIVE DISTRIBUTED FLAG ARCHITECTURE Jan 16, 2017 Abandoned
Array ( [id] => 11606503 [patent_doc_number] => 20170123806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'METHOD FOR DEPENDENCY BROADCASTING THROUGH A SOURCE ORGANIZED SOURCE VIEW DATA STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/408311 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 9897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408311 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408311
Method for dependency broadcasting through a source organized source view data structure Jan 16, 2017 Issued
Array ( [id] => 13268927 [patent_doc_number] => 10146548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Method for populating a source view data structure by using register template snapshots [patent_app_type] => utility [patent_app_number] => 15/408255 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9661 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408255 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408255
Method for populating a source view data structure by using register template snapshots Jan 16, 2017 Issued
Array ( [id] => 13171769 [patent_doc_number] => 10101999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Memory address collision detection of ordered parallel threads with bloom filters [patent_app_type] => utility [patent_app_number] => 15/403101 [patent_app_country] => US [patent_app_date] => 2017-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 4725 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403101 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/403101
Memory address collision detection of ordered parallel threads with bloom filters Jan 9, 2017 Issued
Array ( [id] => 11868232 [patent_doc_number] => 20170235516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'APPARATUS AND METHOD FOR SHUFFLING FLOATING POINT OR INTEGER VALUES' [patent_app_type] => utility [patent_app_number] => 15/385825 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14987 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385825 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385825
APPARATUS AND METHOD FOR SHUFFLING FLOATING POINT OR INTEGER VALUES Dec 19, 2016 Abandoned
Array ( [id] => 11989191 [patent_doc_number] => 20170293346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'VARIABLE-LENGTH INSTRUCTION BUFFER MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 15/382467 [patent_app_country] => US [patent_app_date] => 2016-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10500 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15382467 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/382467
Variable-length instruction buffer management Dec 15, 2016 Issued
Array ( [id] => 13240741 [patent_doc_number] => 10133569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture [patent_app_type] => utility [patent_app_number] => 15/379515 [patent_app_country] => US [patent_app_date] => 2016-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 28715 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15379515 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/379515
Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture Dec 14, 2016 Issued
Array ( [id] => 12735310 [patent_doc_number] => 20180136937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => EFFICIENT RANDOM NUMBER GENERATION FOR UPDATE EVENTS IN MULTI-BANK CONDITIONAL BRANCH PREDICTOR [patent_app_type] => utility [patent_app_number] => 15/364257 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364257 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364257
Efficient random number generation for update events in multi-bank conditional branch predictor Nov 29, 2016 Issued
Array ( [id] => 16200784 [patent_doc_number] => 10725947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Bit vector gather row count calculation and handling in direct memory access engine [patent_app_type] => utility [patent_app_number] => 15/364149 [patent_app_country] => US [patent_app_date] => 2016-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 22454 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364149 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364149
Bit vector gather row count calculation and handling in direct memory access engine Nov 28, 2016 Issued
Array ( [id] => 11501503 [patent_doc_number] => 20170075688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'DATA TRANSFER BUS COMMUNICATION USING SINGLE REQUEST TO PERFORM COMMAND AND RETURN DATA TO DESTINATION INDICATED IN CONTEXT TO ALLOW THREAD CONTEXT SWITCH' [patent_app_type] => utility [patent_app_number] => 15/360014 [patent_app_country] => US [patent_app_date] => 2016-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3090 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15360014 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/360014
Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch Nov 22, 2016 Issued
Array ( [id] => 11530966 [patent_doc_number] => 20170090944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'PARALLEL DATA PROCESSING APPARATUS, SYSTEM, AND METHOD' [patent_app_type] => utility [patent_app_number] => 15/359127 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13857 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359127 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/359127
Parallel data processing apparatus, system, and method Nov 21, 2016 Issued
Array ( [id] => 11445145 [patent_doc_number] => 20170046166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'BRANCH SYNTHETIC GENERATION ACROSS MULTIPLE MICROARCHITECTURE GENERATIONS' [patent_app_type] => utility [patent_app_number] => 15/341161 [patent_app_country] => US [patent_app_date] => 2016-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5900 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15341161 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/341161
Branch synthetic generation across multiple microarchitecture generations Nov 1, 2016 Issued
Array ( [id] => 11473807 [patent_doc_number] => 20170060590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'BRANCH SYNTHETIC GENERATION ACROSS MULTIPLE MICROARCHITECTURE GENERATIONS' [patent_app_type] => utility [patent_app_number] => 15/341119 [patent_app_country] => US [patent_app_date] => 2016-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5900 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15341119 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/341119
Branch synthetic generation across multiple microarchitecture generations Nov 1, 2016 Issued
Array ( [id] => 15373261 [patent_doc_number] => 10528349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Branch synthetic generation across multiple microarchitecture generations [patent_app_type] => utility [patent_app_number] => 15/293318 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5687 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15293318 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/293318
Branch synthetic generation across multiple microarchitecture generations Oct 13, 2016 Issued
Array ( [id] => 13120327 [patent_doc_number] => 10078517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-18 [patent_title] => Methods and apparatus for signal flow graph pipelining in an array processing unit that reduces storage of temporary variables [patent_app_type] => utility [patent_app_number] => 15/238429 [patent_app_country] => US [patent_app_date] => 2016-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 59 [patent_no_of_words] => 30801 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15238429 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/238429
Methods and apparatus for signal flow graph pipelining in an array processing unit that reduces storage of temporary variables Aug 15, 2016 Issued
Array ( [id] => 14917771 [patent_doc_number] => 10430205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Locking/unlocking CPUs to operate in safety mode or performance mode without rebooting [patent_app_type] => utility [patent_app_number] => 15/225342 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2838 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225342 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225342
Locking/unlocking CPUs to operate in safety mode or performance mode without rebooting Jul 31, 2016 Issued
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